• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.3
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• pp.6-11
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• 1977

The noise behavior of the Schottky Barrier Gate FET has been investigated by the use of noise equivalent circuit. It has been found that an additional noise source has to be taken into account in the GaAs SBGFET's biased in the pinch-off region; the intervalley scattering noise and the hot electron noise. In this paper, a noise equivalent circuit has been used to determine the noise parameter which was taken into account influence of the saturation velocity of carrier and parasitic resistance.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.775-778
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• 1987

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bais shows both positive and negative resistance characteristics depending on the gate threhold voltage and gate-to source bias voltage. In this study, the decision method of the internal temperature measurement by $V_{GS}$ and $V_{DS}$ are presented.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.153-155
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• 2002

Trench sate CB-BRT:TC-BRT의 최대 제어 가능 전류(Maximum Controllable Current)에 영향을 미치는 설계 변수들을 조사하였다. 최대 제어 가능 전류를 결정하는 중요 설계 변수들로 트렌치 깊이, 핑거 게이트 길이, 메인 게이트 길이, 트렌치 밀도를 고려하였다. TC-BRT의 실험적 결과를 기존의 BRT와 CB-BRT의 결과와 비교하였다. 최대 제어 가능 전류는 트렌치 깊이와 트렌치 밀도가 증가하고 메인 게이트 길이가 감소할수록 증가하였으며 핑거 게이트 길이에 대해서는 큰 영향을 받지 않았다. 핑거 게이트가 있는 TC-BRT가 없는 것에 비해 최대 제어 가능 전류가 약 15% 높게 나타났다. 트렌치 밀도가 작을 때는 핑거 게이트에 의한 영향이 두드러지고 트렌치 밀도가 높아질수록 트렌치 게이트의 역할이 증가하였다.

• ETRI Journal
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• v.43 no.6
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• pp.1113-1129
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• 2021

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

• Journal of the Korean Society of Safety
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• v.33 no.4
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• pp.1-7
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• 2018

This paper is analyzed for the thermal characteristics(1 year) of the 6 components(DC breaker, DC filter(including capacitor and discharge resistance), IGBT(Insulated gate bipolar mode transistor), AC filter, AC breaker, etc.) of a photovoltaic power generation-based PCS(Power conditioning system) below 20 kW. Among the modules, the discharge resistance included in the DC filter indicated the highest heat at $125^{\circ}C$, and such heat resulting from the discharge resistance had an influence on the IGBT installed on the rear side the board. Therefore, risk priority through risk priority number(RPN) of FMEA(Failure modes and effects analysis) sheet is conducted for classification into top 10 %. According to thermal characteristics and FMEA, it is necessary to pay attention to not only the in-house defects found in the IGBT, but also the conductive heat caused by the discharge resistance. Since it is possible that animal, dust and others can be accumulated within the PCS, it is possible that the heat resulting from the discharge resistance may cause fire. Accordingly, there are two options that can be used: installing a heat sink while designing the discharge resistance, and designing the discharge resistance in a structure capable of avoiding heat conduction through setting a separation distance between discharge resistance and IGBT. This data can be used as the data for conducting a comparative analysis of abnormal signals in the process of developing a safety device for solar electricity-based photovoltaic power generation systems, as the data for examining the fire accidents caused by each module, and as the field data for setting component management priorities.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.211-216
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• 2003

In this paper, characteristics of Ta-Ti alloy was studied as a gate electrode for NMOS devices to replace the widely used polysilicon. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method using two of Ta and Ti targets. The sputtering power of each metal target was 100W. To compare with Ta-Ti, Ta deposited with a 100W sputtering power was fabricated as well. In order to investigate the thermal/chemical stability of the Ta-Ti alloy gate, the alloy was annealed at $600^{\circ}C$ with rapid thermal annealer. No appreciable degradation of the device was observed. Also the results of electrical analysis showed that the work function of Ta-Ti metal alloy was about 4.1eV which was suitable for NMOS devices and sheet resistance of alloy was lower than that of polysilicon.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1789-1796
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• 2012

In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.