• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.49-51
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• 2006

A new data line reduction driving method was developed for high pixel density LCoS microdisplays. Its pixel structures and its corresponding gate line waveform were proposed, too. This idea can fulfill the increasing demand for higher resolution LCoS. In this method, no additional AC power is dissipated, and no more horizontal line time is needed. So this method can be applied to the high resolution microdisplay devices. It prefers being applied to the reflective liquid crystal on silicon microdisplays because of the pixel structure asymmetry and PMOS transistor switches used.

• Journal of IKEEE
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• v.27 no.3
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• pp.273-279
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• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1565-1567
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• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.6
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• pp.7-13
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• 2015

The production processes were reviewed through the injection analysis of the shift lever as a core component of an auto lever installed in the automatic transmission of cars. The injection analysis was carried out for the shift lever and rod among the components in a shift lever module. The shift lever and rod are designed for injection molding with the insertion of a tube, a pin cable plate, and a steel rod for securing the strength of the product. The charging time, failure of injection molding, weld line, air trap, and deformation were reviewed according to this insert. Analyses on various gate positions were carried out for reviewing the cultivation and deformation of fiber around major components, such as the generation section of manipulation feeling and assembly section, so that optimal gate conditions might be reviewed and reflected in the mold design. Finally, we plan to compare the analysis results with the production of trial products.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.15 no.5
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• pp.109-116
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• 2016

Polymethyl methacrylate is commonly used in the outer lens of automotive rear lamps. However, if the lens warps above the allowable limit, it may lead to faulty connection with the housing, and failure of the assembly. This study investigated the effects of gate diameter and cooling line distance in the mold design for automotive outer lens. The optimal gate diameter and cooling line distance to minimize the warp of the outer lens were derived as 3.0 mm and 50-60 mm respectively, and the cooling temperature to minimize warp was shown to be $60-80^{\circ}C$ (mold surface temperature $48-67^{\circ}C$). A higher cooling temperature may somewhat mitigate the warp, but is undesirable because it may cause injection molding problems, such as sinks. A mold was constructed matching the optimal design and the produced lens properties, particularly the degree of warp, were comparable with the CAE predictions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.149-158
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• 1995

This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1157-1162
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• 2007

In this paper, E-TDLNN(Expanded-Tapped Delay Line Neural Network) method is suggested to make the model of power amplifier effectively. This method is the one for making the model of power amplifier through the study in neural network to the target value, the measured output spectrum of power amplifier, after adding the external value factor, gate bias, as an invariant input to the TDLNN method which suggested the memory effect of power amplifier effectively. To prove the validity of suggested method, the data at 2 points, 3.45 V and 3.50 V of gate bias range $3.4{\sim}3.6V$ with the 0.01 V step change, are studied and the predicted results at the gate bias 3.40 V, 3.48 V, 3.53 V and 3.60 V shows good coincidence with the measured values.

• Journal of IKEEE
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• v.24 no.1
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• pp.364-367
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• 2020

This paper presents the off-grid PV-ESS system of sequential voltage control method applied to OR logic gate. The conventional off-grid PV-ESS system with the low-voltage series connection has problems due to capacity expansion. To solve these problems, this paper proposes a noble PV-ESS system with high efficiency and low cost by applying sequential voltage control technique of the high-voltage series connection of analog circuit type. The input voltage of DC to AC inverter can be converted from the low-voltage by the combinations of series connection of the conventional cascaded 24V solar cell unit modules to the high-voltage of 384V in battery. The output voltage of the battery was 384V as the each input voltage of three phase DC to AC inverter, and the each output voltage of three phase 10kW DC to AC inverter is designed to be AC380V@60Hz as the line to line rms voltage value. To prove the validity of the theoretical analysis by PSIM simulation, the operating characteristics of sequential voltage control system with OR logic gate were confirmed through experiment results.