• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of Information Display
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• v.7 no.1
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• pp.1-6
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• 2006

A 10" carbon nanotube field emission display device was fabricated with a novel structure with a hopping electron spacer (HES) by screen printing technique. HES plays a role of preventing the broadening of electron beams emitted from carbon nanotubes without electrical discharge during operation. The structure of the novel tetrode is composed of carbon nanotube emitters on a cathode electrode, a gate electrode, an extracting electrode coated on the top side of a HES, and an anode. HES contains funnel-shaped holes of which the inner surfaces are coated with MgO. Electrons extracted through the gate are collected inside the funnel-shaped holes. They hop along the hole surface to the top extracting electrode. In this study the effects of the addition of HES on emission characteristics of field emission display were investigated. An active ozone treatment for the complete removal of residues of organic binders in the emitter devices was applied to the field emission display panel as a post-treatment.

• Journal of the Korean Vacuum Society
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• v.10 no.2
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• pp.189-193
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• 2001

We have characterized physical and electrical properties of W-TiN stacked gate electrode structure with TiN as a diffusion barrier of fluorine. As the $N_2/Ar$ gas ratio increased during sputter deposition, TiN thin films became N-rich, and the resistivity of the films increased. However, the resistivity of W-TiN stacked gate reduced as a result of the crystallization of tungsten with the increase of $N_2/Ar$ gas ratio. On the other hand, tungsten in W-TiN stacked gate structure have the (100)-oriented crystalline structure although TiN films were subjected to annealing at high temperature (600~$800^{\circ}C$). Leakage currents of W-TiN gate MOS capacitors were less than $10^{-7}\textrm{/Acm}^2$ and also were lowered by the order of 2 compared with those of pure W gate electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.10
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• pp.668-672
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• 2014

Carbon nanotubes(CNT) has chemical stability and great sensitivity characteristics. In particular, the gas sensor required characteristics such as rapid, selectivity and sensitivity sensor. Therefore, CNT are ideal materials to gas sensor. So, we fabricated the NOx gas sensors of MOS-FET type using the MWCNT (multi-walled carbon nanotube). The fabricated sensor was used to detect the NOx gas for the variation of $V_{gs}$(gate-source voltage) and electrode changed electrode spacing=30, 60, 90[${\mu}m$]. The gas sensor absorbed with the NOx gas molecules showed the decrease of resistance, and the sensitivity of sensor was increased by magnification of electrode spacing. Furthermore, when the voltage($V_{gs}$) was applied to the gas sensor, the decrease in resistance was increased. On the other hand, the sensor sensitivity for the injection of NOx gas was the highest value at the electrode spacing $90[{\mu}m]$. We also obtained the adsorption energy($U_a$) using the Arrhenius plots by the reduction of resistance due to the voltage variations. As a result, we obtained that the adsorption energy was increased with the increment of the applied voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• ETRI Journal
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• v.45 no.1
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.9-15
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• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.2
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.