• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.10a
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• pp.286-290
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• 2001

This paper presents a full-digital low-level controller for a robotic material transfer system which has been developed for a computer-integrated manufacturing model plant. Compared to conventional analog or hybrid type controllers in current industrial environments, this controller system has some advantages such as strong noise-immunity, easy control algorithm implementation, etc The servo-controller consists of two modules, a position controller and a DC servo motor driver. The position controller operates position feedback routines by receiving position encoder data and sending control outputs to the driver. The position controller is implemented in a full-digital way using a recently introduced microcontroller. The DC servomotor driver controls speeds and torques. The driver consists of a micro-controller and insulated-gate-bipolar-transistors (IGBT). The micro-controller provides control signals, and the IGBT's amplifies the control signals and sends them to the motor.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1029-1032
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• 2005

A 262K-color QVGA LTPS AMLCD was developed. This panel has integrated gate driver and data multiplexer (1:3) by p_Si LTPS TFT process. The commercialized driver IC was adopted to implement this display. Fine image quality, low powerconsumption and cost-efficiency feature make the panel be suitable for mobile application.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1168-1171
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• 2007

Integrating systems on TFT-LCD panels is more and more popular for the mobile display application. However, it may not be necessary to use LTPS TFT devices. A-Si TFTs are used to integrate systems on TFT-LCD panels, especially scan (gate) drivers. To further reduce the chip size of driver IC, the triplegate pixel structure is developed. Therefore, the number of the source lines is reduced to 1/3 times.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.108-110
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• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1292-1294
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• 1996

The general output circuit for PWM output is pushpull using a complimentary MOSFET. The gate driver coupled directly at gate can switch easy upto a high frequency. However, a high reverse recovery current and parastic components make a oscillation output. This paper analyses this phenomenon and proposes a novel output circuit preventing the oscillation.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.1
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• pp.71-77
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• 2008

This paper proposes an Electronic Throttle Body (ETB) model considering a non-linearity of DC motor driver which is integrated with a H-bridge and a gate driver. A propagation delay and reverse recovery time of switching components cause non-linear characteristic of DC motor driver. This non-linearity affects not only the amateur voltage of DC motor, but also entire behaviour and parameters of ETB. In order to analyze the behavior of ETB more accurately, this non-linear effect of DC motor driver is modeled. The developed ETB model is validated by use of the step response and ramp response experiments, and it shows relatively accurate results compared with linear DC motor driver model.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.96-102
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• 2009

This paper deals with gate drive and power IC for high power devices(600V/200A and 1200V/150A). The proposed gate driver provides high gate driving capability (4 A source, 8 A sink), and over-current protected by means of power transistor desaturation detection. In addition, soft-shutdown function is added to reduce voltage overshoots due to parasitic inductance. This gate drive If is designed, fabricated, and tested using the Dongbu hitek 0.35um BCDMOS process.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.99-104
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• 1999

The large scale industry needs high voltage converters. Therefore series connection of power semiconductor devices is necessary. It is important to prevent the overvoltage from being induced across a device above ratings by the proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by controlling the slope of collector voltage under the turn-off transient in the series connected IGBTs. The proposed gate control scheme which senses the collector voltage and controls the gate signal actively limits the overvoltage. The new series connected IGBT gate driver is made and its validity is verified by the experimental results in the series connected IGBT circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.176-183
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• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.