• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Korean Journal of Materials Research
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• v.2 no.4
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• pp.285-292
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• 1992

Ultrathin(8nm) oxynitride (SiOxNy) film have been formed on Si(100) by rapid thermal processing(RTP) in $O_2$and $N_2$O as reactants. Compared with conventional furnace $O_2$ oxide, the oxynitride dielectrics shows better characteristics of I-V and TDDB, and less flat-band voltage shift. The oxynitride has a behavior of Fowler-Nordheim tunneling in the region of V 〉${\varphi}_0$ simialr to pure Si$O_2$oxide. The relative dielectric constant of oxynitride is higher than that of conventional pure oxide. Excellent diffusion harrier property to dopant(B$F_2$) is also observed. Nitrogen depth profiles by SIMS, AES, and XPS show nitrogen pile - up at Si$O_2$/Si interface, which can explain the improved properties of oxynitride dielectrics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• Korean Journal of Materials Research
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• v.15 no.2
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• pp.139-142
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• 2005

[ $ZrO_2$ ] gate dielectric thin films were deposited by radio frequency (rf)-magnetron sputtering and its structure, surface morphology and electrical peoperties were studied. As the oxygen flow rate increases, the surface becomes smoother. The experimental results indicate that a high temperature annealing is desirable since it improves the electrical properties of the $ZrO_2$ gate dielectric thin films by decreasing the number of interfacial traps at the $ZrO_2/Si$ interface. The carrier transport mechanism is dominated by the thermionic emission.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.487-490
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• 2006

We propose a new method to achieve well-defined surface properties of the polymeric gate dielectrics without using SAM technique and inserting another organic/inorganic buffer layer. Pentacene thin film transistors(OTFTs) fabricated with the polyimide gate insulators with different side chain structures were demonstrated. Further, a relationship between the surface properties (surface morphology, surface energy, etc) of the films and the performance of OTFTs have investigated, which will be given in more detail in presentation.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.653-655
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• 2003

Using stacked organic gate insulators and active layer of pentacene deposited at elevated temperatures, pentacene-based organic thin-film transistors(OTFTs) with improved electrical characteristics have been fabricated. Stacked PVP(Polyvinylphenol)-polystyrene gate insulators could compensate the demerits and take advantage of the merits of each other [1]. Also, for the better device performance, moderate substrate heating and high deposition rate of pentacene active layer was adopted [2, 3].

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1932-1938
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• 2003

We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.972-973
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• 2007

Relationships between field effect mobility and grain size on pentacene thin-film transistors with $polyimide/SiO_2$ gate dielectrics have been studied. 6 kinds of polyimide were used as surface treatment gate dielectric layer. Grain size of the pentacene thin film were between 5 and $30\;{\mu}m$ and depended on the polyimide. The field effect mobility were also depended on the polyimide and the those values were from 0.027 to $0.69\;cm^2/(Vs)$. The field effect mobility tends to increase with increasing the grain size. Precursor type polyimide containing polyamic acid show better mobility of $0.69\;cm^2/(Vs)$ than soluble type polyimide. Bias stress characteristics in air are discussed in the basis of the grain size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1266-1272
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• 2012

An InGaZnO thin film transistor with different gate lengths and widths have been fabricated and their device degradations with device sizes have been also performed after negative gate bias stress. The threshold voltage and subthreshold swing have been decreased with decrease of gate length. However, the threshold voltages were increased with the decrease of gate lengths. The transfer curves were negatively shifted after negative gate stress and the threshold voltage was decreased. However, the subthreshold swing was not changed after negative gate stress. This is due to the hole trapping in the gate dielectric materials. The decreases of the threshold voltage variation with the decrease of gate length and the increase of gate width were believed due to the less hole injection into gate dielectrics after a negative gate stress.