• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제30A권9호
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권1호
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• pp.185-192
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• 1995

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제8권4호
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제24권12A호
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• pp.2008-2014
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• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1597-1599
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• 2007

In TFT-LCD, mura is a defect which degrades the display quality. The resistance difference between gate lines is the main cause of H-Block mura. Two methods could eliminate this defect. A thinner gate layer or gate fan-out pattern decrease mura level. H-Block mura has been reduced after implementing the new schemes.

• Journal of Biosystems Engineering
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• 제34권2호
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• pp.95-105
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• 2009

A method was proposed which employed control of the drop location of fertilizer particles on a spinner disc to optimize the spread pattern uniformity. The system contained an optical sensor as a feedback mechanism, which measured discharge velocity and location, as well as particle diameters to predict a spread pattern of a single disc. Simulations showed that the feed gate adaptation algorithm produced high quality patterns for any given application rate in the dual disc spreader. The performance of the feed gate control method was assessed using data collected from a Sulky spinner disc spreader. The results showed that it was always possible to find a spread pattern with an acceptable CV lower than 15%, even though the spread pattern was obtained from a rudimentary flat disc with straight radial vanes. A mathematical optimization method was used to find the initial parameter settings for a specially designed experimental spreading arrangement, which included the feed gate control system, for a given flow rate and swath width. Several experiments were carried out to investigate the relationship between the gate opening and flow rate, disc speed and particle velocity, as well as disc speed and predicted landing location of fertilizer particles. All relationships found were highly linear ($r^2$ > 0.96), which showed that the time-of-flight sensor was well suited as a feedback sensor in the rate and uniformity controlled spreading system.

• Journal of IKEEE
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• 제3권1호
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제33A권3호
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Proceedings of the KIPE Conference
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.108-110
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• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.