• Journal of Sensor Science and Technology
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• v.21 no.6
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Journal of Navigation and Port Research
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• v.41 no.3
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• pp.119-126
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• 2017

As container vessels get larger, container terminals are also likely to grow. The problem that arises is that the growing volume should be handled in the same amount of time as before. Container terminals are introducing an automation system in order to overcome the limitations of existing manual methods and to continuously reduce operating expenses. Because, Manual handling of carrying containers gate in and out of terminals causes inaccurate data, which results in confusion. An alternative is for containers to be labeled with barcodes that can be scanned into a system with a scanner, but this takes quite a long time and is inconvenient. A RFID system, also known as a gate automation system, can solve these problems by reducing the time of gate management with a technology that detects number identification plates, helping operators more efficiently perform gate management work. Having said that, with this system, when container damage is detected, gate operators make and keep documents manually. These documents, which are insufficient evidence in proving container damage, result in customer claims. In addition, it is difficult for gate operators and other workers to manage containers, exposing them to danger and accidents. This study suggests that if an automation system is introduced at gates, containers can be managed by a video storage system in order to better document damage The video system maintains information on container damage, allowing operators the ability to search for videos they need upon customer request, also allowing them to be better prepared for customer claims. In addition, this system reduces necessary personnel and risk of accidents near gates by integrating a wide range of work.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.169-170
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• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.

• Journal of Power System Engineering
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• v.11 no.1
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• pp.45-50
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• 2007

Acoustic emission technology is applied to diagnosis the internal leak and operating conditions of the major valves at nuclear power plants. The purpose of this study is to verify availability of the acoustic emission as in-situ diagnosis method. In this study, acoustic emission tests are performed when the pressurized high temperature steam flowed through gate valve(1st stage reheater valve) and glove valve(main steam dump valve) on the normal size of 4 and 8". The valve internal leak diagnosis system for practical field was designed. The acoustic emission method was applied to the valves at the site, and the background noise was measured for the abnormal plant condition. To improve the reliability, a judgment of leak on the system was used various factors which are AE parameters, trend analysis, signal level analysis and RMS(root mean square) analysis of acoustic signal emitted from the valve operating condition internal leak.

• Journal of Multimedia Information System
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• v.6 no.4
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• pp.323-328
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• 2019

In this paper, a method of constructing an advanced sequential circuit over finite fields is proposed. The method proposed an algorithm for assigning all elements of finite fields to digital code from the properties of finite fields, discussed the operating characteristics of T-gate used to construct sequential digital system of finite fields, and based on this, formed sequential circuit without trajectory. For this purpose, the state transition diagram was allocated to the state dependency code and a whole table was drawn showing the relationship between the status function and the current state and the previous state. The following status functions were derived from the status function and the preceding table, and the T-gate and the device were used to construct the sequential circuit. It was confirmed that the proposed method was able to organize sequential digital systems effectively and systematically.

• Journal of the Korean Society of Radiology
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• v.14 no.5
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• pp.529-535
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• 2020

Geant4 is compatible with the Windows operating system in C++ language use, enabling interface functions that link DICOM or software. It was simulated to address the basic structure of the simulation using Geant4/Gate code and to specifically verify the density composition and lung cancer process in the human phantom. It was visualized using the Gate Graphic System, i.e. openGL, Ray Tracer: Ray Tracing by Geant4 Tracing, and using Geant4/Gate code, lung cancer is modeled in the human phantom area in 3D, 4D to verify the simulation progress. Therefore, as a large number of new functions are added to the Gate Code, it is easy to implement accurate human structure and moving organs.

• ETRI Journal
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• v.38 no.2
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.1-8
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• 2005

In this paper, design and implement 60W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of Doherty power amplifier is distinguishable; however implementation of assistance amplifer is difficult, though. To solve the problem, therefore, GCHD (Gate Control Hybrid Doherty) power amplifier is embodied to gate bias adjusament circuit of assistance amplifier to General Doherty power amplifier. Experiment result shows that $2.11\~2.17GHz$, 3GPP operating frequency band, with 62.55 dB gain, PEP output is 50,76 dBm, W-CDMA average power is 47.81 dBm, and -40.05 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than general power amplifier.