• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.27-31
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• 2018

The effect of $NH_3$ plasma passivation on the chemical and electrical characteristics of ALD HfAlO dielectric on the InGaAs substrate was investigated. The results show that $NH_3$ plasma passivation exhibit better electrical & chemical performance such as much lower leakage current, lower density of interface trap(Dit) level, and low unstable interfacial oxide. $NH_3$ plasma passivation can effectively enhance interfacial characteristics. Therefore $NH_3$ plasma passivation improved the HfAlO dielectric performance on the InGaAs substrate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.245-245
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• 2008

In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 센서학회지
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• 제24권3호
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• pp.165-168
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• 2015

We demonstrated low-voltage organic thin-film transistors (OTFTs) with bilayer insulators, high-k polymer and low temperature crosslinkable polymer, on a flexible plastic substrate. Poly (vinylidene fluoridetrifluoroethylene) (P(VDF-TrFE)) and poly (2-vinylnaphthalene) are used for high-k polymer gate insulator and low temperature crosslinkable polymer insulators, respectively. The mobility of flexible OTFTs is $0.17cm^2/Vs$ at gate voltages -5 V after bending operation.

• EDISON SW 활용 경진대회 논문집
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• 제4회(2015년)
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• pp.357-364
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• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

• 한국정보통신학회논문지
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• 제20권10호
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• pp.1927-1934
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• 2016

본 논문에서는 일반적인 실리콘 기반 n-MOSFET(n-type Metal Oxide Semiconductor Field Effect Transistor)의 절연 산화막 계면에서 방사선으로부터 유발되는 누설전류 경로를 차단하기 위하여 I형 게이트 n-MOSEFT 구조를 제안하였다. I형 게이트 n-MOSFET 구조는 상용 0.18um CMOS(Complementary Metal Oxide Semiconductor) 공정에서 레이아웃 변형 기법을 이용하여 설계되었으며, ELT(Enclosed Layout Transistor)와 DGA(Dummy Gate-Assisted) n-MOSFET와 같은 레이아웃 변형 기법을 사용한 기존 내방사선 전자소자의 구조적 단점을 개선하였다. 따라서, 기존 구조와 비교하여 반도체 칩 제작에서 회로 설계의 확장성을 확보할 수 있다. 또한, 내방사선 특성 검증을 위하여 TCAD 3D(Technology Computer Aided Design 3-dimension) tool을 사용하여 모델링과 모의실험을 수행하였고, 그 결과 I형 게이트 n-MOSFET 구조의 내방사선 특성을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• Journal of Information Display
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• 제11권4호
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• pp.165-168
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• 2010

A solution-processed multicomponent oxide, yttrium hafnium zinc oxide (YHZO), was synthesized and deposited as a gate insulator. The YHZO film annealed at $600^{\circ}C$ contained an amorphous phase based on the results of thermogravimetry, differential thermal analysis, and X-ray diffraction. The electrical characteristics of the YHZO film were analyzed by measuring the leakage current. The high dielectric constant (16.4) and high breakdown voltage (71.6 V) of the YHZO films resulted from the characteristics of $HfO_2$ and $Y_2O_3$, respectively. To examine if YHZO can be applied to thin-film transistors (TFTs), indium gallium zinc oxide TFTs with a YHZO gate insulator were also fabricated. The desirable characteristics of the YHZO films when used as a gate insulator show that the limitations of the general binary-oxide-based materials and of the conventional vacuum processes can be overcome.