• Transactions on Electrical and Electronic Materials
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• 제16권3호
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1301-1305
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• 2005

The performance of OTFT with $PVP-TiO_2$ composite, as a gate insulator, is reported, including the effect of surfactant for synthesizing the composite material. According to our investigation results, it was one of critical issues to prevent the aggregation of $PVP-TiO_2$ particles during the synthesis process. From this point of view, $PVP-TiO_2$ particles were treated using Tween80, as a surfactant, and we could reduce the aggregated $PVP-TiO_2$ clusters. As a result, the OTFT with the composite insulator showed the threshold voltage of about -8.3 V and the subthreshold slope of about 1.5 V/decade, which are the optimized properties compared to those of OTFTs with bare PVP, in this study. It is thought that these characteristic improvements are originated from the increase in the dielectric constant of the PVP-based insulator by compositing with high-k particles.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• 반도체디스플레이기술학회지
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• 제6권4호
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• pp.69-73
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• 2007

The MIM(metal-insulator-metal) capacitors with the Al/PMMA/ITO/Glass structures were manufactured according to various PMMA concentration of 1, 2, 4, 6, 8 wt%. The lowest leakage current and the largest capacitance were found to be 2.3 pA and 1.2 nF, respectively, for the device with 2 wt% PMMA concentration. The measured capacitance of the devices was almost same values with the calculated one. The optimum film thickness was obtained at the value of 48 nm, showing that the capacitance and leakage current were 1.92 nF, 0.3 pA at 2 wt%, respectively. From this experiment, the PMMA gate insulator films can be applicable to the organic thin film transistors.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.359-363
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• 2005

유기 박막트랜지스터 (OTFT)를 제작하기 위하여 게이트 절연막으로서 PVP 계통의 유기막을 갖는 MIM(metal-insulator-metal)구조의 유기 절연층 소자를 제작하였다. 유기 절연층의 형은 ITO/Glass 기판위에 polyvinyl 계열의 PVP(poly-4-vinylphenol)를 용질로, PGMEA (propylene glycol monomethyl ether acetate)를 용매로 사용하여 co-polymer PVP를 제조하였다. 또한 열경화성 수지인 poly(melamine-co-formaldehyde)를 경화제로 사용하여 cross-linked PVP 절연막을 합성하였다. 유기 절연층의 전기적 특성은 co-polymer PVP 소자에 비해 cross-link 방식으로 제조된 소자에서 약 300 pA의 낮은 누설전류와 상대적으로 낮은 잡음전류의 특성을 나타내었다. 또한 cross-linked PVP 절연막에서 보다 양호한 표면형상 (거칠기)이 관찰되었으며 정전용량 값은 약 0.11${\~}$0.18 nF의 값을 나타내었다.

• 접착 및 계면
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• 제22권4호
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• pp.144-152
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• 2021

유기반도체와 게이트 절연체 간 계면전하이동을 이해하는 것은 고성능 유기메모리, 고안정성 유기전계효과 트랜지스터 (이하 유기트랜지스터) 개발에 기여할 수 있다. 본 연구에서는 계면 간 전하이동의 특이거동, 즉 홀전하가 유기반도체에서 고분자절연체로 이동되어 편재화되는 것이 편재화 준위간의 커플링에 의해 비선형적으로 가속화될 수 있음을 최초로 밝혀내었다. 이의 규명을 위해 rubrene 단결정과 Mylar 절연체를 기반으로 한 유기트랜지스터를 vacuum lamination 공정으로 제작하여 반도체-절연체 계면의 반복적인 전사와 박리에도 안정적인 소자를 개발하였다. Rubrene 단결정과 Mylar film의 표면을 각각 광유도 산소 확산법과 UV-오존 처리를 통해 결함을 생성시켰다. 그 결과, 계면 간 전하이동과 이에 의한 바이어스 스트레스 효과가 rubrene과 Mylar가 가진 편재화 준위 간 커플링에 의해 비선형적으로 급격하게 가속화되었음을 관측하였다. 특히, rubrene 단결정에 있는 적은 밀도의 편재화 준위가 계면 간 전하이동을 촉진하는데 가교역할을 함을 밝혀내었다

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• 한국광과학회:학술대회논문집
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• 한국광과학회 2006년도 정기총회 및 제13회 학술대회 논문 초록
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• pp.38-38
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• 2006

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.1-5
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• 2011

본 논문에서는 AlGaN/GaN HEMT의 항복 전압 특성 향상을 위해 2차원 소자 시뮬레이터를 통하여 게이트 필드 플레이트 구조를 최적화하였다. 필드플레이트 길이, 절연체 종류, 절연체 두께 변화 등의 세가지 변수를 이용하여 시뮬레이션을 진행하였으며 그에 따른 전기장 분포의 변화와 항복전압 특성을 확인하였다. 필드플레이트 구조를 최적화 시킴으로서 게이트 에지부분과 필드플레이트 에지부분에 집중 되어있던 전기장이 효과적으로 분산된다. 그에 따라 애벌런치 효과가 줄어들게 되어 항복전압 특성이 향상된다. 결론적으로 최적화된 게이트 필드플레이트 구조는 일반적인 구조에 비해 항복특성을 약 300% 이상 향상시킬 수 있다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1466-1469
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• 2008

We have fabricated 2.5 inch QQCIF AM-OLED panel driven by ZnO-TFT on a plastic substrate for the first time. The number of photo mask for the whole panel process was 5 and the TFT structure was top gate with active protection layer as a first gate insulator. Optimizing the process for the substrate buffer layer, active layer, ZnO protection layer, and gate insulator was key factor to achieve the TFT performance enough to drive OLED. The ZnO TFT has mobility of $5.4\;cm^2/V.s$, turn on voltage of -6.8 V, sub-threshold swing of 0.39 V/decade, and on/off ratio of $1.7{\times}10^9$. Although whole process temperature is below $150^{\circ}C$ to be suitable for the plastic substrate, performance of ZnO TFT was comparable to that fabricated at higher temperature on the glass.