• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.

• Journal of Information Display
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• v.11 no.3
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• pp.95-99
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• 2010

A series of new dielectric polymers with phenyl, epoxy, and carboxylicacid functional groups was prepared via free-radical polymerization. The effect of such dielectric polymers with various functional groups on the performance of OTFT was investigated. The nonpolar groups of terpolymer made the surface of the dielectric layer more hydrophobic and improved the crystal growth of pentacene on the gate insulator, resulting in higher mobility. By controlling the functional group, the electric characteristics of OTFT performance was varied, with $0.00017-0.15\;cm^2/V{\cdot}s$ mobility.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.05a
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• pp.84-87
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• 1988

cIn this paper. we evaluate the breakdown and TDDB characteristics of ammonia free ECVD SiN films which studied widely as a gate insulator to substitute the silicon dioxide because of it's superior film characteristics with the merit of low temperature process. And also, we propose a new statistical model by introduce a dispersion factor in the traditional Weibull statistics. From the comparison of experimental result, and simulation one, try to dock the breakdown mechanism and statistical analysis.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1590-1592
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• 2002

In this work the electrical characteristics of organic TFTs using organic insulator and flexible polyester substrate have been investigated. Pentacene and PVP(polyvinylphenol) are used as an active semiconducting layer and dielectric layer respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $1{\times}10^{-6}$ Torr and at a deposition rate of $0.5{\AA}$/sec, and PVP was spin-coated. Aluminium and gold were used for gate and source/drain electrodes. 0.1mm thick flexible polyester substrate was used instead of glass or silicon wafer.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.98-99
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• 2014

질산산화법(nitric acid oxidation method)은 저온에서 안정적인 산화막을 형성하는 직접산화공정으로 azeotropic point(68 wt%)인 120도 이하의 온도에서 산화막을 형성한다. 120도에서 형성한 질산산화막은 CVD법으로 형성한 산화막 보다 낮은 누설전류밀도(leakage current density)를 나타낸다. 또한 질산의 농도가 증가함에 따라 형성한 산화막의 누설전류밀도가 감소하며, 이는 열산화법으로 형성한 산화막 보다 낮다. 질산산화의 낮은 누설전류밀도는 형성한 산화막의 높은 원자 밀도와 낮은 계면준위밀도에 의한 것으로 이 특성을 이용하여 게이트 절연막(gate insulator)과 태양전지의 passivation막으로 응용되고 있다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.166-168
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• 2016

This paper introduces about the structure guide lines of pocket tunneling Field effect transistor. As the pocket length or thickness increase, on-current $I_{on}$ increases. As the pocket thickness is less than 3nm, subthreshold swing (SS) increase. As the dielectric constants of the gate insulator increases, the performance of on-current and subthreshold swing enhances.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1189-1192
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• 2009

Short channel a-Si:H TFT devices with Cu electrodes have been investigated. Short channel TFTs are defined by new plasma etch process. When the channel length becomes shorter, the TFT characteristics (threshold voltage, off current, sub threshold voltage, etc.,) are degraded. These degraded characteristics can be improved through the hydrogen plasma treatment and new gate insulator structure. Using these processes, 15.0 inch XGA LCD panel was fabricated successfully where the channel length of the TFT devices was about 2.5 micrometers.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.8-11
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• 2007

The new technologies in mobile display developed in SEC are briefly reviewed. For a differentiation, SEC's LTPS line is based on SLS (Sequential Lateral Solidification) technology. In this paper, the characteristics of SEC's SLS in recent and future mobile displays were discussed. The microstructure produced by SLS crystallization is dependent on SLS process conditions such as mask design, laser energy density, and pulse duration time. The microstructure and TFT (Thin Film Transistor) performance are closely related. For an optimization of TFT performance, SLS process condition should be adjusted. Other fabrication processes except crystallization such as blocking layer, gate insulator deposition and cleaning also affect TFT performance. Optimized process condition and tailoring mask design can make it possible to produce high quality AMOLED devices. The TFT non-uniformity caused by laser energy density fluctuation could be successfully diminished by mixing technology.