• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 추계학술대회 초록집
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• pp.219-220
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• 2009

이번 실험에서는 TiN의 건식 식각 특성을 연구하기 위해 $BCl_3/Ar/N_2$ 유도 결합플라즈마를 이용하였다. BCl3와 Ar의 가스 비율이 $BCl_3$ (5 sccm)/Ar (15 sccm)/N (4 sccm) 인 상황에서 RF power와 DC bias, 그리고 process pressure을 식각변수로 설정하였다. TiN의 식각률은 Alpha-step 500으로 측정하였고 표면의 식각 후 화학반응은 XPS로 측정하였다.

• 전자공학회논문지A
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• 제29A권10호
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• pp.29-34
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• 1992

JFET's with gate lengths ranging from 1$\mu$m to 8.3$\mu$m are successfully fabricated on InP substrate where the long haul (1.3$\mu$m~8.3$\mu$m) OEIC's(OptoElectronic Integrated Circuits) have been made. The pn junction of InP JFET's is made by co-implantation and RTA process. JFET's have etched-mesa-gate structure and the maximum gm larger than 90mS/mm was measured and this is the highest record in JFET's of such structure without S/D n$^{+}$ ion implantation. To maintain maximum g$_m$ should be well controlled the overetch of n-layer which inevitably occurs during etching off the unused p-layer. The I-V characteristic is checked during p-layer etch, for this purpose. A dc voltage gain of 11 is obtained from a preamplifier circuit thus fabricated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.328-331
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• 1988

Sealed Interface Local Oxidation (SILO) technology has been investigated using a nitride/oxide/nitride three-layered sandwich structure. P-type silicon substrate was either nitrided by rapid thermal processing, or silicon nitride was deposited by LPCVD method. A three-layered sandwich structure was patterned either by reactive ion etch (RIE) mode or by plasma mode. Sacrificial oxidation conditions were also varied. Physical characterization such as cross-section analysis of field oxide, and electrical characterization such as gate oxide integrity, junction leakage and transistor behavior were carried out. It was found that bird's beak was nearly zero or below 0.1um, and the junction leakages in plasma mode were low compared to devices of the same geometry patterned in RIE mode, and gate oxide integrity and transistor behavior were comparable. Conclusively, SILO process is compatible with conventional local oxidation process.

• Transactions on Electrical and Electronic Materials
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• 제3권3호
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.145-148
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• 2007

The authors report on the fabrication of thin film transistors (TFTs) that use amorphous indium-gallium-zinc oxide (a-IGZO) channel and have the channel length (L) and width (W) patterned by dry etching. To prevent the plasma damage of active channel, a 100-nm-thckness $SiO_{x}$ by PECVD was adopted as an etch-stopper structure. IGZO TFT (W/L=10/50${\mu}m$) fabricated on glass exhibited the high performance mobility of $35.8\;cm^2/Vs$, a subthreshold gate voltage swing of $0.59V/dec$, and $I_{on/off}$ of $4.9{\times}10^6$. In addition, 4.1” transparent QCIF active-matrix organic light-emitting diode display were successfully fabricated, which was driven by a-IGZO TFTs.

• 한국정보통신학회논문지
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• 제11권6호
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• pp.1099-1103
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• 2007

본 연구는 기존의 방식으로 만든 비정질 실리콘 박막 트랜지스터의 제조공정에서 발생되는 결함에 대한 원인을 분석하고 해결함으로써 수율을 증대시키고 신뢰성을 개선하고자한다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝 하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거한다. 그 위에 Cr층을 증착한 후 패터닝하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 이렇게 제조한 박막 트랜지스터에서 생기는 문제는 주로 광식각공정시 PR의 잔존이나 세척시 얇은 화학막이 표면에 남거나 생겨서 발생되며, 이는 소자를 파괴시키는 주된 원인이 된다. 그러므로 이를 개선하기 위하여 ashing이나 세척공정을 보다 엄격하게 수행하였다. 이와 같이 공정에 보다 엄격한 기준의 세척과 여분의 처리 공정을 가하여 수율을 확실히 개선 할 수 있었다.

• 한국컴퓨터정보학회논문지
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• 제9권1호
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• pp.9-15
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• 2004

본 논문에서는 드레인 부근의 채널 영역에서 접합 전계를 줄이는 WSW(Wrap Side Wall) 구조의 소자를 제안하였다. WSW구조의 소자 제작은 첫 번째 게이트를 식각한 후에 NM1(N-type Minor1) 이 온주입을 하고 다시 질화막을 덮어 식각함으로서 만들어진다. 새로운 WSW구조는 전계를 줄이기 위한 버퍼층으로 되어 있으며 WSW소자와 LDD구조의 소자 수명을 비교하였으며 핫-캐리어 열화 특성도 분석하였다. 또한 AC 핫-캐리어 열화를 칩 상에서 평가하기 위해 펄스 발생기, 레벨 시프터, 주파수 분배기를 포함한 테스트 패턴 회로를 설계하였다. 이러한 것은 AC와 DC 스트레스간의 핫-캐리어 열화 조건이 AC와 DC 스트레스 모두 동일한 물리적 메커니즘을 지닌다는 것을 알 수 있었다. 따라서 일반적으로 회로 동작 조건 하에서 DC 핫-캐리어 열화 특성을 토대로 AC 소자 수명도 예측할 수 있었다.

• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.447-452
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• 1998

The selective dry etching of GaAs to Al\ulcornerGa\ulcornerAs using $BCI_3/SF_6$ gas mixture in electron cyclotron resonance(ECR) plasma is investigated. A selectivity of GaAs to AlGaAs of more than 100 and maximum etch rate of GaAs are obtained at a gas ratio $SF_6/BCI_3+SF_6$ of 25%. We verified the formation of $AlF_3$ on $Al_{0.25}Ga_{0.75}As$from the Auger spectra which enhanced the etch selectivity. In order to investigate surface damage of AlGaAs caused by ECR plasma, we performed a low temperature photoluminescence(PL) measurement as a function of RF power. As the RF power. As the RF power increases, the PL intensity decreases monotonically from 50 to 100 Wand then repidly decreases until 250 W. This behavior is due to surface damage by plasma treatment. This dry etching technique using $BCI_3/SF_6$ gas mixture in ECR plasma is suitable for gate recess formation on the GaAs based pseudomorphic high electron mobility transistor(PHEMT)

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.681-685
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• 2012

We investigated the dry etching characteristics of TiN in $TiN/Al_2O_3$ gate stack using a inductively coupled plasma system. TiN thin film is etched by BCl3/He plasma. The etching parameters are the gas mixing ratio, the RF power, the DC-bias voltages and process pressures. The highest etch rate is in $BCl_3/He$ (25%:75%) plasma. The selectivity of TiN thin film to $Al_2O_3$ is pretty similar with $BCl_3/He$ plasma. The chemical reactions of the etched TiN thin films are investigated by X-ray photoelectron spectroscopy. The intensities of the Ti 2p and the N 1s peaks are modified by $BCl_3$ plasma. Intensity and binding energy of Ti and N could be changed due to a chemical reaction on the surface of TiN thin films. Also we investigated that the non-volatile byproducts such as $TiCl_x$ formed by chemical reaction with Cl radicals on the surface of TiN thin films.