• Proceedings of the Materials Research Society of Korea Conference
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• 2001.05a
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• pp.82-82
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• 2001

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.280-280
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• 2008

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.11a
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• pp.75-75
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• 2002

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• ETRI Journal
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• v.33 no.6
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• pp.887-896
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• 2011

We investigated the effects of a gate dielectric and its solvent on the characteristics of top-gated organic field-effect transistors (OFETs). Despite the rough top surface of the inkjet-printed active features, the charge transport in an OFET is still favorable, with no significant degradation in performance. Moreover, the characteristics of the OFETs showed a strong dependency on the gate dielectrics used and its orthogonal solvents. Poly(3-hexylthiophene) OFETs with a poly(methyl methacrylate) dielectric showed typical p-type OFET characteristics. The selection of gate dielectric and solvent is very important to achieve high-performance organic electronic circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.187-187
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• 2012

Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.9
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• pp.736-742
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• 1991

N$^{+}$poly gate NMOSFETs and p$^{+}$ poly gate (surface type) PMOSFETs with three different gate oxides(SiO2, NO, and ONO) were fabricated. The rapid thermal nitridation and reoxidation techniques have been applied to gate oxide formation. The current drivability of the ONO NMOSFET shows larger values than that of the SiO2 NMOSFET. The snap-back occurs at a lower drain voltage for SiO$_2$ cases for ONO NMOSFET. Under the maximum substrate current bias conditions, hot-carrier effects inducting threshold voltage shift and transconductance degradation were investigated. The results indicate that ONO films exhibit less degradation in terms of threshold voltage shift. It was confirmed that the ONO samples achieve good improvement of hot-carrier immunity. In a SiO$_2$ SC-PMOSFET, with significant boron penetration, it becomes a depletion type (normally-on). But ONO films show excellent impurity barrier properties to boron penetration from the gate.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.461-463
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• 2009

We report on the fabrication of ZnO-based thin-film transistor (TFT) inverters with top and bottom gate structures with $Al_2O_3$ dielectrics grown by atomic layer deposition (ALD). Since the top gate ZnO-based TFT showed somewhat lower field effect mobility than that of the bottom gate device, our ZnO-based TFT inverters were designed with identical dimensions for both channels. This TFT inverter device demonstrated an high voltage gain at a low supply voltage of 5 V and clear dynamic behavior.