• 제목/요약/키워드: Gate Design

검색결과 1,594건 처리시간 0.031초

Intelligent Power Module의 플로팅 게이트 전원 공급을 위한 전하 펌프 회로의 설계 (Design of Charge Pump Circuit for Intelligent Power Module of Floating Gate Power Supply)

  • 임정규;김석환;서은경;정세교
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2005년도 전력전자학술대회 논문집
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    • pp.421-423
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    • 2005
  • A bootstrap circuit for floating power supply has the advantage of being simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. Hence, this paper deals with a design of charge pump circuit for a floating gate power supply of an IPM. The operation of the proposed circuit applied by three-phase inverter system for driving induction motor are verified through the experiments.

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새로운 정전용량 계산식물 이용한 대면적 .고화질 TFT-LCD의 화소 특성 시뮬레이션 (Simulations of Pixel Characteristics for Large Size and High Qualify TFT-LCD using a new sophisticated Capacitance Formulas)

  • 윤영준;정순신;김태형;박재우;최종선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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    • pp.613-616
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    • 1999
  • An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

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입.출력 버퍼방식을 이용한 대용량 케이블 점검 시스템 설계 및 구현 (Design and Implementation of Large Capacity Cable Checking System using an I/O Buffer Method)

  • 양종원
    • 한국군사과학기술학회지
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    • 제5권2호
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    • pp.103-115
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    • 2002
  • This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

통도사 대웅전과 영산회상의 상관관계에 대한 고찰 (Relations between the meanings of Tongdosa temple and Darma talk on Vulture peak)

  • 김개천
    • 한국실내디자인학회논문집
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    • 제32호
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    • pp.21-27
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    • 2002
  • Tongdo temple is one of the representative temples that the Buddhistic outlook on the universe and the world is well expressed. This article will discuss the expressive and symbolic meaning that Darma talk on vulture peak signifies by contemplating the road leading from Ilju gate to Buddha's hall in terms of Karam arrangement of the temple and the unique plane delineation of Bulee gate. It seems that Darma talk on vulture peak is related to the reason why there is no Buddha statue in Buddha's hall and why the name of the mountain has been changed considering the resemblance of its shape to India's Youngchook mountain. The present study will take this relation into account and will show the religious faith and architectural meaning with respect to this relationship.

RS(23,17) 리드-솔로몬 복호기 설계 (Design of a RS(23,17) Reed-Solomon Decoder)

  • 강성진
    • 한국정보통신학회논문지
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    • 제12권12호
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    • pp.2286-2292
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    • 2008
  • 본 논문에서는 MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) 시스템에서 사용되는 RS(23,17) 부호에 대한 복호기의 최적 구조를 제안하고, 설계하였다. 제안된 복호기 구조는 파이프 라인 구조를 갖는 수정된 유클리드(Modified Euclidean) 알고리즘을 사용하며, MB-OFDM 시스템에 최적화되어 작은 복호 지연(latency) 및 하드웨어 복잡도를 가진다. 제안된 복호기는 Verilog HDL을 사용하여 구현되었고, 삼성 65nm library를 이용하여 합성하였다. 350MHz로 합성했을 때 timing violation이 발생하지 않았기 때문에, 실제 ASIC을 제작해도 250MHz까지 동작하며, gate count는 20,710로 나타났다.

An efficient reliability estimation method for CNTFET-based logic circuits

  • Jahanirad, Hadi;Hosseini, Mostafa
    • ETRI Journal
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    • 제43권4호
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    • pp.728-745
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    • 2021
  • Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

무선 전기성문전도 측정기 설계 (Design of a Wireless Electrical Gate Conductivity Measurment Device)

  • 엄상희;김기련;김광년;남재현
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2021년도 추계학술대회
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    • pp.311-312
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    • 2021
  • 성대 질환과 관련한 측정 기술은 기술 축적이 늦은 상태이며, 전기성문전도(electroglotograph : EGG) 측정 장비는 외산에 의존적이다. 본 논문에서는 발성에 있어서 중요한 성대의 진동 상태, 즉 성대의 접촉양상을 간편하게 측정하여 모니터링할 수 있는 착용형 무선 전기성문전도 측정 단말기를 설계하고자 하였다.

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서울 동북지역 관문 상징육교 디자인 (A symbolical footbridge design as a gate in east-north Seoul)

  • 박선우;송태섭
    • 한국공간구조학회:학술대회논문집
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    • 한국공간구조학회 2005년도 춘계학술발표회 및 정기총회 2권1호(통권2호)
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    • pp.83-88
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    • 2005
  • This paper deals with design processing for in a east- north Seoul. The pedestrian cross over main street through Seoul and Uijongbu. For resonable beautiful footbridge it need to technical mind and art. The method of process for this footbridge approached in both the field of science and art. Starting with structure planning it need to cooperate both engineering and architect. To design a resonable and economical structural master piece, everyone must solve a gaps between technology and art for structural design.

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QCA 기반의 효율적인 PCA 구조 설계 (Design of PCA Architecture Based on Quantum-Dot Cellular Automata)

  • 신상호;이길제;유기영
    • 한국항행학회논문지
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    • 제18권2호
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    • pp.178-184
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    • 2014
  • PCA에 기반을 둔 CMOS 소자 기술은 메모리 혹은 ALU 회로의 구현에 매우 효율적이다. 그러나 CMOS 소자 스케일링 기술의 한계로 인하여 이를 해결할 수 있는 새로운 기술의 필요성이 대두되었고, 양자점 셀룰러 오토마타(QCA; quantum-dot cellular automata)는 이를 해결할 수 있는 기술로 등장했다. 본 논문에서는 QCA에 기반을 둔 효율적인 PCA 구조를 설계한다. 설계하는 PCA 구조에서의 D 플립플롭과 XOR 논리게이트는 기존에 제안되었던 회로를 사용하고, 입력 제어 스위치와 규칙 제어 스위치는 QCA에 기반을 두고 새롭게 설계한다. 설계된 PCA 구조는 QCA디자이너를 이용하여 시뮬레이션을 수행하고, 그 결과를 기존의 것과 비교 및 분석하여 설계된 구조의 효율성을 확인한다.

공리적 개념을 적용한 사출성형 시스템의 최적설계 (The Optimization of Injection Molding System Using Axiomatic Approach)

  • 김종헌;이종수;차성운
    • 대한기계학회논문집A
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    • 제27권6호
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    • pp.1020-1027
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    • 2003
  • A traditional mold design has been conducted by an experience-based trial and error, whereby the mold designer would decide the gate locations and processing conditions based on the caring characteristics and its functional requirements. The paper suggests an optimal gate location and processing conditions in the injection molding using a global search method referred to as micro genetic algorithm( ${\mu}$ GA). ${\mu}$ GA yields the optimal solution with a small size of population without respect to design variables for saving time that is needed to calculate the fitness of many individuals. Due to the reason, the paper uses a commercial analysis package of injection molding(CAPA) to analysis a state of flux. In addition to that, axiomatic approach .is applied in the beginning of design. It is a useful method to draw a well-organized and reasonable idea to handle a problem.