• Title/Summary/Keyword: Gate Design

Search Result 1,594, Processing Time 0.025 seconds

Studies on the Fabrication and Characteristics of PHEMT for mm-wave (mm-wave용 전력 PHEMT제작 및 특성 연구)

  • Lee, Seong-Dae;Chae, Yeon-Sik;Yun, Gwan-Gi;Lee, Eung-Ho;Lee, Jin-Gu
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.38 no.6
    • /
    • pp.383-389
    • /
    • 2001
  • We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

  • PDF

Design of a 512b Multi-Time Programmable Memory IPs for PMICs (PMIC용 512비트 MTP 메모리 IP설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
    • /
    • v.9 no.1
    • /
    • pp.120-131
    • /
    • 2016
  • In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

Electrical analysis of Metal-Ferroelectric - Semiconductor Field - Effect Transistor with SPICE combined with Technology Computer-Aided Design (Technology Computer-Aided Design과 결합된 SPICE를 통한 금속-강유전체-반도체 전계효과 트랜지스터의 전기적 특성 해석)

  • Kim, Yong-Tae;Shim, Sun-Il
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.12 no.1 s.34
    • /
    • pp.59-63
    • /
    • 2005
  • A simulation method combined with the simulation program with integrated circuit emphasis (SPICE) and the technology computer-aided design (TCAD) has been proposed to estimate the electrical characteristics of the metal-ferroelectric-semiconductor field effect transistor (MFS/MFISFET). The complex behavior of the ferroelectric property was analyzed and surface potential of the channel region in the MFS gate structure was calculated with the numerical TCAD method. Since the calculated surface potential is equivalent with the surface potential obtained with the SPICE model of the conventional MOSFET, we can obtain the current-voltage characteristics of MFS/MFISFET corresponding to the applied gate bias. Therefore, the proposed method will be very useful for the design of the integrated circuits with MFS/MFISFET memory cell devices.

  • PDF

Development of a Tool for the Electrical Analysis and Design of TFT/LCD System Package (TFT/LCD 시스템 패키지 전기적 특성 분석 및 설계도구의 구현)

  • Yim, Ho-Nam;Jee, Yong
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.32A no.12
    • /
    • pp.149-158
    • /
    • 1995
  • This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

  • PDF

Optimization of Valve Gates Locations Using Automated Runner System Modeling and Metamodels (유동 안내부 모델링 자동화 및 근사모델을 이용한 자동차용 도어트림의 밸브 게이트 위치 최적화)

  • Joe, Yong-Su;Park, Chang-Hyun;Pyo, Byung-Gi;Rhee, Byung-Ohk;Choi, Dong-Hoon
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.22 no.2
    • /
    • pp.115-122
    • /
    • 2014
  • Injection pressure is one of factors that influence part quality. In this paper, injection pressure was minimized by optimizing valve gate locations. In order to perform design optimization, MAPS-3DTM (Mold Analysis and Plastic Solution-3D) was used for injection mold analysis and PIAnOTM (Process Integration, Automation and Optimization) was used as process integration and design optimization. Also we adapted meta models based on design of experiments for efficiency. By using introduced methodology, we were able to obtain a result so that maximum injection pressure reduced by 28% compared to the initial design. And the validity of the proposed method could also be demonstrated.

Design of Pagoda Park, Seoul (탑골공원 설계)

  • 김성균
    • Journal of the Korean Institute of Landscape Architecture
    • /
    • v.29 no.2
    • /
    • pp.42-49
    • /
    • 2001
  • This design proposal was presented to a design competition for renovation of the Pagoda Park, located in Chongro-2ga, Chongro-gu, Seoul, where the first ˝Manse˝ (hurrah) Movement fighting against Japanese colonization, broke out on March 1st, 1919. The park has been considered to be the first modern park in Korea also. The objectives for the design were to make a sacred place to commemorate the 3.1 ˝Manse˝ Movement, to preserve and symbolically memorialize historic remains of the old ˝Wongaksa˝ Temple, an to provide natural and rest areas for citizen. For the space composition, three axes symbolic of, ´freedom and independence´, ´mercy´, and ´nature´, were created. For the freedom and independence axis, exiting facilities, such as statures and monuments related to the 3.1 Movement, were relocated centering around the octagonal pavilion, which was the starting point for the movement, to give order of the site. For the ercy axis, symbols of traditional temple structures, such as, ´Iljugate´-´Pian bridge´-´Chongwang gate´-´Haetal gate´-Pagoda-Buddhist sanctum, were created to symbolize the temple remains and placeness. For the nature axis, tree groves, walking trails, and rest areas for citizen were provided around the site. As a whole the design provided structural orders from secular spaces outside to sacred spaces inside.

  • PDF

Numerical Analysis in Hydrograph Determination for Sluice Gate installed Levee (배수통문이 설치된 제방의 설계수위파형결정에 관한 수치해석)

  • Kim, Jin-Man;Choi, Bong-Hyuck;Oh, Eun-Ho;Cho, Won-Beom
    • Journal of the Korean Geosynthetics Society
    • /
    • v.14 no.4
    • /
    • pp.1-9
    • /
    • 2015
  • According to national regulations and its commentary, such as Rivers Design Criteria & Commentary (KWRA, 2009), Foundation Structure Guideline and its Commentary(MLTM, 2014 and KGS, 2009), the integrity evaluation of river levee includes slope stability evaluation of both riverside/protected low-land and piping stability evaluation with respect to foundation and levee body along with water level conditions. In this case the design hydro-graph can be the most important input factor for the integrity evaluation, however it is fact that the national regulations do not provide any proper determination methods regarding hydro-graph. The authors thus executed an integrity evaluation of sluice gate in levee by changing each hydro-graph factor, including rising ordinary water level, lasting flood water level, falling water level, and flood frequency, in order to suggest a determination method of reasonable hydro-graph. As a result, the authors suggested that at least over 57 hours of rising ordinary water level and over 53 hours of lasting flood water level should be considered for the design hydro-graph of sluice gate in levee at Mun-san-jae.

A Study on the Part Shrinkage in Injection Molded Annular Shaped Product for Glass Reinforced Polycarbonate (유리섬유 강화 폴리카보네이트의 환상형상부품 사출성형시 성형수축에 관한 연구)

  • Lee, Mina;Lyu, Min-Young
    • Elastomers and Composites
    • /
    • v.48 no.4
    • /
    • pp.300-305
    • /
    • 2013
  • Part shrinkage in injection molding is inevitable phenomenon. Thus, it is necessary not only study on the reducing part shrinkage but characterization of part shrinkage. In this study, part shrinkage in injection molded 2.5 dimensional annular shaped specimens has been studied using glass fiber reinforced PC. Annular shaped specimens were designed with various sizes of outer diameter and thickness. Injection temperature, packing time and packing pressure were selected for operational conditions. Profile variations of outer and inner diameters of molded specimens for various operational conditions were investigated. Sizes of outer and inner diameters of injection molded specimens were smaller than the sizes of mold. Part shrinkage decreased as outer diameter and thickness increased. Part shrinkage showed anisotropic behavior and it depended upon gate location. Subsequently, molded specimens were not circular but oval in shape, and showed the largest shrinkage in the direction of gate. It was realized that the mold design such as gate design is important to control the shape of molded products.

Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors (나노와이어 junctionless 트랜지스터의 문턱전압 및 평탄전압 모델링과 소자설계 가이드라인)

  • Kim, Jin-Young;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.12
    • /
    • pp.1-7
    • /
    • 2011
  • In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

VORTEX STRUCTURE IN THE SCOUR HOLE BY GATE OPENING OF HYDRAULIC STRUCTURE

  • Kim, Jin-Hong;Choe, Jae-Wan
    • Water Engineering Research
    • /
    • v.1 no.1
    • /
    • pp.83-92
    • /
    • 2000
  • Jet flow can occur by gate opening at downstream of a hydraulic structure such as weir of drainage gate. If the stream bed is not hard or the bed protection is not sufficient, vortex erosion occurs and a resulting scour hole will be formed due to the high shear stress of the jet flow. Once the scour hole is formed, a vortex occurs in ti and this vortex causes additional erosion. If this erosion continues and reaches to the hydraulic structure, it can undermine the bottom of the hydraulic structure and this will lead to failure of the structure itself. Thus, it is necessary to define the physical features of the vortex structure in the scour hole for the design of the bed protection. This study presents the turbulent vortex structure in the scour hole by the gate opening of the hydraulic structure. Characteristics of vortex motion, circulation, vortex scale and vortex were analyzed through experiments. Experimental results of the vortex velocity were compared with theoretical ones. From these, circulation and vortex scale were obtained with known values of inflow depth, inflow velocity and scale of scour hole

  • PDF