• Title/Summary/Keyword: Gate Design

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A Low Power Design of H.264 Codec Based on Hardware and Software Co-design

  • Park, Seong-Mo;Lee, Suk-Ho;Shin, Kyoung-Seon;Lee, Jae-Jin;Chung, Moo-Kyoung;Lee, Jun-Young;Eum, Nak-Woong
    • Information and Communications Magazine
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    • v.25 no.12
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    • pp.10-18
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    • 2008
  • In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

A Performance-Oriented Intra-Prediction Hardware Design for H.264/AVC

  • Jin, Xianzhe;Ryoo, Kwangki
    • Journal of information and communication convergence engineering
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    • v.11 no.1
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    • pp.50-55
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    • 2013
  • In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

Design of Control System for Hydraulic Cylinders of a Sluice Gate Using Fuzzy PI Algorithm (퍼지 PI를 이용한 배수갑문용 유압실린더 제어기 설계)

  • Hui, Wuyin;Choi, Chul-Hee;Choi, Byung-Jae;Hong, Chun-Pyo;Yoo, Seog-Hwan;Kwon, Yeung-Tae
    • Journal of the Korean Institute of Intelligent Systems
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    • v.20 no.1
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    • pp.109-115
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    • 2010
  • A main technology of opening and closing a sluice gate is accurate synchronous and position control for the two cylinders when they are moving with the sluice gate together over 10[m]. Since the supply flow and supply pressure of cylinders are not constant and a nonlinear friction force of the piston in cylinders exists, a difference will be made between the displacement of two cylinders. This difference causes the sluice gate to deform and abrade, and even it may be out of order. In order to solve this problem we design two kinds of fuzzy PI controllers. The former is for a position control of two cylinders, the latter is for their synchronous control. We show some simulation results compare the performance of fuzzy PI controller to the conventional PID controller.

Evaluation of GaN Transistors Having Two Different Gate-Lengths for Class-S PA Design

  • Park, Jun-Chul;Yoo, Chan-Sei;Kim, Dongsu;Lee, Woo-Sung;Yook, Jong-Gwan
    • Journal of electromagnetic engineering and science
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    • v.14 no.3
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    • pp.284-292
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    • 2014
  • This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

Implementation of a Radiation-hardened I-gate n-MOSFET and Analysis of its TID(Total Ionizing Dose) Effects

  • Lee, Min-Woong;Lee, Nam-Ho;Jeong, Sang-Hun;Kim, Sung-Mi;Cho, Seong-Ik
    • Journal of Electrical Engineering and Technology
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    • v.12 no.4
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    • pp.1619-1626
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    • 2017
  • Electronic components that are used in high-level radiation environment require a semiconductor device having a radiation-hardened characteristic. In this paper, we proposed a radiation-hardened I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistors) using a layout modification technique only. The proposed I-gate n-MOSFET structure is modified as an I-shaped gate poly in order to mitigate a radiation-induced leakage current in the standard n-MOSFET structure. For verification of its radiation-hardened characteristic, the M&S (Modeling and Simulation) of the 3D (3-Dimension) structure is performed by TCAD (Technology Computer Aided Design) tool. In addition, we carried out an evaluation test using a $Co^{60}$ gamma-ray source of 10kGy(Si)/h. As a result, we have confirmed the radiation-hardened level up to a total ionizing dose of 20kGy(Si).

The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications (Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계)

  • 정훈호;권오경
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.176-184
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    • 1996
  • To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

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The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

  • Li, Jing;Ning, Ning;Du, Ling;Yu, Qi;Liu, Yang
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.99-106
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    • 2012
  • For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

A Novel Air-Bridge Type Gate-Data Line Inter-Crossing to Reduce Signal Delay for Large Size AMLCD (대면적 AMLCD의 신호 지연 감소를 위해 Air-gap을 갖는 게이트-데이터 라인 교차 구조)

  • Park, Jin-Woo;Kang, Ji-Hoon;Lee, Min-Cheol;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.12
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    • pp.768-772
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    • 1999
  • A new TFT-LCD panel with air-bridge type gate to data line inter-crossing has been proposed and its characteristics have been measured. The proposed structure has air-gap between gate and data line inter-crossing. This air-bridge TFT-LCD panel has very small capacitance between gate and data line. The new panes structure achieves 9 times fast signal propagation compared with conventional panel, which enables to have enough design margin for 20-inch diagonal and larger size UXGA panel. We have examined thermal and mechanical durability of new panel to verify applicability for commercial AMLCD production. After TEOS and polyimide passivation, this panel withstood a thermal stress at $250^{\circ}C$ and a mechanical stress during the rubbing process.

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Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

  • Vanitha, P.;Balamurugan, N.B.;Priya, G. Lakshmi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.585-593
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    • 2015
  • In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

2D Quantum Effect Analysis of Nanoscale Double-Gate MOSFET (이차원 양자 효과를 고려한 극미세 Double-Gate MOSFET)

  • Kim, Ji-Hyun;Son, Ae-Ri;Jeong, Na-Rae;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.15-22
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    • 2008
  • The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.