• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.1
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• pp.1-7
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• 2017

Today only 5-15% (approximately 1 in 10 persons) of persons with disabilities in need globally have access to assistive products which assist or replace the impaired functioning[1]. GATE (Global Cooperation on Assistive Technology) is a WHO global initiative for cooperation of stakeholders to cope with current and future challenges in product design, pricing, delivery and services, as well as medical and social system, expert training, and policies. This paper introduces the concept of WHO GATE to improve access to assistive technology for everyone by the cooperation with global key stakeholders.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.1-6
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• 2003

In this paper, a sub-harmonic dual-gate FET mixer is suggested to improve the isolation characteristic between LO and RF ports of an unbalanced mixer. The mixer was designed by using single-gate FET cascode structure and driven by the second harmonic component of LO signal. A dual-gate FET mixer has good isolation characteristic since RF and LO signals are injected into gatel and gate2, respectively. In addition, the isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer due to the large frequency separation between the LO and RF frequencies. As RF power was -30 ㏈m and LO power was 0 ㏈m, the designed mixer yielded the -47.17 ㏈m LO-to-RF leakage power level, 10 ㏈ conversion gain, -2.5 ㏈m OIP3, -12.5 ㏈m IIP3 and -1 ㏈m 1 ㏈ gain compression point. Since the LO-to-RF leakage power level of the designed mixer is as good as that of a double-balanced mixer, the sub-harmonic dual-gate FET mixer can be utilized instead.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.122-122
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• 2010

A Static Induction Thyristor (SI-Thyristor) has a great potential as power semiconductor switch for pulsed power or high voltage applications with fast turn-on switching time and high switching stress endurance (di/dt, dV/dt). However, due to direct commutation between gate driver and SI-Thyristor, it is difficult to design optimal gate driver at the aspect of impedance matching for fast gate current driving into internal SI-Thyristor. Thus, to penetrate fast positive gate current into steady off state of the SI-Thyristor, it is proposed and proceeded the internal impedance calculation of the SI-Thyristor at steady off state with the gate driver while switching conditions that are indicated applied gate voltage, $V_{GK}$ and applied high voltage across anode and cathode, $V_{AK}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.96-102
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• 2009

This paper deals with gate drive and power IC for high power devices(600V/200A and 1200V/150A). The proposed gate driver provides high gate driving capability (4 A source, 8 A sink), and over-current protected by means of power transistor desaturation detection. In addition, soft-shutdown function is added to reduce voltage overshoots due to parasitic inductance. This gate drive If is designed, fabricated, and tested using the Dongbu hitek 0.35um BCDMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1927-1934
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• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.1
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• pp.35-40
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• 2017

A most important progress in civilization was the introduction of mass production. One of main methods for mass production is die-casting molds. Due to the high velocity of the liquid metal, aluminum die-casting is so complex where flow momentum is critical matter in the mold filling process. Actually in complex parts, it is almost impossible to calculate the exact mold filling performance with using experimental knowledge. To manufacture the lightweight automobile bodies, aluminum die-castings play a definitive role in the automotive part industry. Due to this condition in the design procedure, the simulation is becoming more important. Simulation can make a casting system optimal and also elevate the casting quality with less experiment. The most advantage of using simulation programs is the time and cost saving of the casting layout design. For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_BR2E, Computer Aided Engineering (CAE) simulation was performed with three layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with three models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflows. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.1
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• pp.11-15
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• 1976

In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.804-810
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• 2005

An analytical subthreshold swing (SS) model has been presented for double gate MOSFET(DGMOSFET) in this study. The results calculated by this model are more precise for about 10nm channel length and thickness than those derived from the previous models. The results of this model are compared with Medici simulation to varify the validity of this model, and good agreementes have been obtained. The changes of SS have been investigated for various channel lengths, channel thicknesses and gate oxide thicknesses using this model, given that these parameters are very important in design of DGMOSFET. This demonstrates that the proposed model provides useful data for design of nano-scale DGMOSFET. It is Known that the SS is improved to smaller ratios of channel thickness vs channel length and is smaller in very thin oxides. New gate dielectric materials with high permittivity have to be developed to enable design of nano-scale DGMOSFET.

• Elastomers and Composites
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• v.38 no.4
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• pp.295-302
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• 2003

The amount of shrinkage of injection molded parts is different from operational conditions of injection molding such as injection temperature, injection pressure and mold temperature, and mold design such as gate size. It also varies depending on the presence of crystalline structure in resins. In this study, part shrinkage was investigated for various operational conditions and resins. Poly(butylene terephthalate) (PBT) for crystalline polymer, and polycarbonate (PC) and poly(methyl methacrylate) (PMMA) for amorphous polymers were used. Crystall me polymer showed higher part shrinkage by about three times than that of amorphous polymers. Part shrinkage increased as melt and molt temperatures increased, and injection pressure decreased. Part shrinkage decreased as gate size increased since the pressure delivery is mush easier for larger gate sizes. Part shrinkage at the position close to the gate was larger than that or the position far from gate. This phenomenon might be occur by difference of residual stress.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.447-448
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• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.