• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.136-144
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• 2021

The purpose of this study was to develop and verify a precision transmission error measurement system for a gear pair. The transmission error measurement system of the gear pair was developed as a measurement unit, signal processing unit, and signal analysis unit. The angular displacement for calculating the transmission error of the gear pair was measured using an encoder. The signal amplification, interpolation, and transmission error calculation of the measured angular displacement were conducted using a field-programmable gate array (FPGA) and a real-time processor. A high-pass filter (HPF) was applied to the calculated transmission error from the real-time processor. The transmission error measurement test was conducted using a gearbox, including the master gear pair. The same test was repeated three times in the clockwise and counterclockwise directions, respectively, according to the load conditions (0 - 200 N·m). The results of the gear transmission error tests showed similar tendencies, thereby confirming the stability of the system. The measured transmission error was verified by comparing it with the transmission error analyzed using commercial software. The verification showed a slight difference in the transmission error between the methods. In a future study, the measurement and analysis method of the developed precision transmission error measurement system in this study may possibly be used for gear design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.834-841
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• 2018

A power amplifier for subgigahertz short-range wireless communication using $0.18-{\mu}m$ CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of $2.14mm^2$.

• Journal of IKEEE
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• v.23 no.2
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• pp.425-430
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• 2019

This work describes the design and characterization of a X-band power amplifier (PA) monolithic microwave integrated circuit (MMIC) using a $0.25{\mu}m$ gate length gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed X-band power amplifier MMIC has small signal gain of over 22.7 dB and saturated output power of 43.02 dBm (20.04 W) over the entire band of 9 to 10 GHz. Maximum saturated output power is a 43.84 dBm (24.21 W) at 9.5 GHz. Its power added efficiency (PAE) is 41.0~51.24% and the chip dimensions are $3.7mm{\times}2.3mm$, generating the output power density of $2.84W/mm^2$. The developed GaN power amplifier MMIC is expected to be applied in a variety of X-band radar applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.401-404
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• 2016

This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.7
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• pp.63-72
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• 2019

The purpose of this study is to apply the types of urban street pattern and the shape of streets to the master plan of a religious community complexes. The street pattern is a framework of urban structure and to understand the urban structure is helpful to understand the nature of urban streets. By analysing the precedent researches, the types of street patterns are classified as a serial pattern, a branching pattern, a grid pattern and a web pattern. The street patterns are hierarchically composed and classified as a differential development and sequential development. There are boundaries and gates where the street space is differentiated to the more private level. The urban streets continue to the architectural streets such as arcades, deck streets, corridors, lobbies and halls. The purposes and results of the master plan of this religious community complexes are as follows. 1) The school area, housing area and service area are properly separated and connected. They are separated by the building masses and connected by the street space in between. 2) The street pattern of this complexes is a serial pattern where the streets are the center of each functional building groups. The entry square is divided by the symbolic building. The one branch is school street and the other is living street. These streets are combined again to the festival street. 3) The architectural streets are organically related to the urban streets. 4) Each street spaces are of adequate form according to its properties as a place. 5) There are boundaries or gates such as a gab between buildings, posts, arches and deck streets according to the relationship between streets.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.