• 한국자동차공학회논문집
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• 제20권4호
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• pp.46-51
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• 2012

Injection pressure, an important factor in filling process, should be minimized to enhance injection molding quality. Injection pressure can be controlled by valve gate open timing. In this work, we decided the valve gate open timing to minimize the injection pressure. To solve this design problem, we integrated MAPS-3D (Mold Analysis and Plastic Solution-3Dimension), a commercial injection molding CAE tool, to PIAnO (Process Integration, Automation and Optimization), a commercial PIDO (Process Integration, and Design Optimization) tool using the file parsing method. In order to reduce computational cost, we performed an approximate optimization using meta-models that replaced expensive computer simulations. At first, we carried out DOE (Design of Experiments) using OLHD (Optimal Latin Hypercube Design) available in PIAnO. Then, we built Kriging models using the simulation results at the sampling points. Finally, we used micro GA (Genetic Algorithm) available in PIAnO. Using the proposed design approach, the injection pressure has been reduced by 13.7% compared to the initial one. This design result clearly shows the validity of the proposed design approach.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2005년도 창립60주년 기념 추계 학술대회
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• pp.221.1-221.1
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• 2005

• Progress in Superconductivity
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• 제4권2호
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• 전자공학회논문지 IE
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• 제47권1호
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• pp.1-5
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• 2010

본 논문은 SOI 저장음 종폭기에서 게이트구조가 핫캐리어에 의한 성능저하에 미치는 영향융 조사하였다. 회로 시뮬레이션은 H-게이트와 T-게이트를 가지는 SOI MOSFET에서 측정된 S-파라미터와 Agilent사의 ADS를 사용하여 스트레스 전후의 H-게이트와 T-게이트 저잡음 증폭기의 성능을 비교하였다. 또한 저잡음 증폭기의 장치 열화와 성능 열화 사이의 관계뿐만 아니라 임피던스 매칭(S11), 잡음 지수와 이득에 관한 저잡음 증폭기의 성능 지수 등을 논의하였다.

• 대한건축학회논문집:계획계
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• 제35권2호
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• pp.73-82
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• 2019

The purpose of this study was to analyze the area of the southern gate in ancient temples. As the southern gate played a role of the front gate, the national or royal ceremonies had been held around the southern gates. The ancient southern gate of temples has had the place for the huge ceremonies such as a royal parade and an inspection of troops. Moreover, this place was recorded in the 'Samkooksagi(三國史記)' as Jeon-Ro(前路). The Southern gate and the Jeon-Ro had been planned together in the front area of the ancient temples, and the gate had been designed to look down the Jeon-Ro. These findings can be verified through the result of a recent excavation at a site of Hwangnyongsa temple in Gyeongju. This research confirmed that the huge ceremonies had been held at the Jeon-Ro including the area of southern gates. Furthermore, a Hwangnyongsa temple is regarded as a concrete case of verifying the composition of the area of Southern gate.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 춘계학술대회논문집
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• pp.363-370
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• 2003

Shrinkage of injection molded parts is different form operational conditions of injection molding such as injection temperature, injection pressure and mold temperature, and mold design such as gate size. It is also various for different resins which have crystalline structure or not. In this study part shrinkage was investigated for various operational condition and resins; PBT for crystalline polymer, and PC and PMMA for amorphous polymer was used in experiment. Crystalline polymer shows higher part shrinkage by about three times than amorphous polymer. Part shrinkage increased as injection temperature and mold temperature increased and injection pressure decreased. Part shrinkage decreased as gate size increased since the pressure delivery is mush easier for large gate size. Part shrinkage according to the gate location was that the position in the part with close to the gate showed large shrinkage and this phenomenon might be occurred by residual stress.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.197-197
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• 1999

Gate oxide 의 두께 감소는 gate의 캐패시턴스를 증가시켜 트랜지스터의 속도를 빠르게 하며, 동시에 저전압 동작을 가능하게 하기 때문에 gate oxide 두께는 MOS 공정 세대가 진행되어감에 따라 계속 감소할 것이다. 이러한 얇은 산화막은 device design에 명시된 두께의 특성을 나타내야 한다. Gate oxide의 두께가 작아질수록 gate oxide와 crystalline silicon간의 계면효과가 박막의 두께의 결정에 심각한 영향을 주기 때문에 정확한 두께 계측이 어렵다. 이러한 영향과 계측방법에 따라서 두께 계측의 차이가 나타난다. XTEM은 사용한 parameter에, Ellipsometer는 refractive index에, MEIS(Medium) Energy Ion Scattering)은 에너지 분해능에, Capacitor-Voltage 측정은 depletion effect에 의해 영향을 받는다. 우리는 계면의 원자분해능 분석에 통상 사용되어온 High Resolution TEM을 이용하여 약 30~70$\AA$ SiO2층의 두께와 계면 구조에 대한 분석을 하여 이를 MEIS와 0.015nm의 고감도를 가진 SE(Spectroscopy Ellipsometer), C-V 측정 결과와 비교하여 가장 좋은 두께 계측 방법을 찾고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• 한국소음진동공학회논문집
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• 제16권4호
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• pp.380-386
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• 2006

ATM is a machine that receives and pays money. The gate module of ATM separates forgeries from bills and changes the transfer direction of bills. In this paper, the dynamic behavior of the gate was analyzed numerically and experimentally. The moment of inertia of the gate lever, the driving force of the solenoid and the spring force were measured, respectively. And the displacements of the plunger, the Input voltage and current were measured experimentally. The measured dynamic behaviors were simulated numerically using Maxwell program which can accommodate the electromagnetic problem of the solenoid. Through the analysis, the design factors were found to make a fast and reliable new ATM gate module.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.822-824
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• 2007

This paper investigated a gate driver circuit with amorphous silicon for mobile TFT-LCD. In the conventional circuit, the fluctuation of the off-state voltage causes the fluctuation of gate line voltages in the panel and then image quality becomes worse. Newly designed gate driver circuit with dynamic switching inverter and carry out signal reduce the fluctuation of the off-state voltage because dynamic switching inverter is holding the off-state voltage and the delay of carry signal is reduced. The simulation results show that the proposed a-Si:H gate driver has low noise and high stability compared with the conventional one.