• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.271-275
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• 2011

In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to $450^{\circ}C$. The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.121-121
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• 2010

ZnO is a promising material for the application of high efficiency light emitting diodes with short wavelength region for its large bandgap energy of 3.37 eV which is similar to GaN (3.39 eV) at room temperature. The large exciton binding energy of 60 meV in ZnO provide provides higher efficiency of emission for optoelectronic device applications. Several ZnO/ZnMgO multiple quantum well (MQW) structures have been grown on various substrates such as sapphire, GaN, Si, and so on. However, the achievement of high quality ZnO/ZnMgO MQW structures has been somehow limited by the use of lattice-mismatched substrates. Therefore, we propose the optical properties of ZnO/ZnMgO multiple quantum well (MQW) structures with different well widths grown on lattice-matched ZnO substrates by molecular beam epitaxy. Photoluminescence (PL) spectra show MQW emissions at 3.387 and 3.369 eV for the ZnO/ZnMgO MQW samples with well widths of 2 and 5 nm, respectively, due to the quantum confinement effect. Time-resolved PL results show an efficient photo-generated carrier transfer from the barrier to the MQWs, which leads to an increased intensity ratio of the well to barrier emissions for the ZnO/ZnMgO MQW sample with the wider width. From the power-dependent PL spectra, we observed no PL peak shift of MQW emission in both samples, indicating a negligible built-in electric field effect in the ZnO/$Zn_{0.9}Mg_{0.1}O$ MQWs grown on lattice-matched ZnO substrates.

• Journal of Sensor Science and Technology
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• v.13 no.2
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• pp.128-132
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• 2004

Short wave infrared (SWIR) photovoltaic devices have been fabricated from metal organic vapour phase epitaxy (MOVPE) grown n- on p- HgCdTe films on GaAs substrates. The MOVPE grown films were processed into mesa type discrete devices with wet chemical etching employed for meas delineation and ZnS surface passivatlon. ZnS was thermally evaporated from effusion cell in an ultra high vacuum (UHV) chamber. The main features of the ZnS deposited from effusion cell in UHV chamber are low fixed surface charge density, and small hysteresis. It was found that a negative flat band voltage with -0.6 V has been obtained for Metal Insulator Semiconductor (MIS) capacitor which was evaporated at $910^{\circ}C$ for 90 min. Current-Voltage (I-V) and temperature dependence of the I-V characteristics were measured in the temperature range 80 - 300 K. The Zero bias dynamic resistance-area product ($R_{0}A$) was about $7500{\Omega}-cm^{2}$ at room temperature. The physical mechanisms that dominate dark current properties in the HgCdTe photodiodes are examined by the dependence of the $R_{0}A$ product upon reciprocal temperature. From theoretical considerations and known current expressions for thermal and tunnelling process, the device is shown to be diffusion limited up to 180 K and g-r limited at temperature below this.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.4
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• pp.229-234
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• 2017

In this study, we fabricated a TFT gas sensor with ZnO nanorods grown by hydrothermal synthesis. The suggested devices were compared with the conventional ZnO film-type TFTs in terms of the gas-response properties and the electrical transfer characteristics. The ZnO seed layer is formed by atomic-layer deposition (ALD), and the precursors for the nanorods are zinc nitrate hexahydrate ($Zn(NO_3)_2{\cdot}6H_2O$) and hexamethylenetetramine ($(CH_2)6N_4$). When 15 ppm of NO gas was supplied in a gas chamber at $150^{\circ}C$ to analyze the sensing capability of the suggested devices, the sensitivity (S) was 4.5, showing that the nanorod-type devices respond sensitively to the external environment. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which showed that the oxygen deficiency of ZnO nanorods is higher than that of ZnO film, and confirms that the ZnO nanorod-type TFTs are advantageous for the fabrication of high-performance gas sensors.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.