• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.3
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• pp.318-326
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• 1996

This study is to investigate a chemical vapor deposition technique of copper film which is expected to be more useful as metallizations of microcircuit fabrication. An experimental equipment was designed and set-up for this study, and a Cu-precursor used that is a metal-organic compound, named (hfac)Cu(I)VTMS ; (hevaflouoroacetylacetonate trimethyvinylsilane copper). Base pressure of the experimental system is in $10^{-6}$ Torr, and the chamber pressure and the substrate temperature can be controlled in the system. Before the deposition of copper thin film, tungsten or titanium nitride film was deposited onto the silicon wafer. Helium has been used as carrier gas to control the deposition rate. As a result, deposition rate was measured as $1,800\;{\AA}/min$ at $220^{\circ}C$ which is higher than the results of previous studies, and the average surface roughness was measured as about $200\;{\AA}$. A deposition selectivity was observed between W or TiN and $SiO_{2}$ substrates below $250^{\circ}C$, and optimum results are observed at $180^{\circ}C$ of substrate temperature and 0.8 Torr of chamber pressure.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1069-1077
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• 2011

In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.146-146
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• 2017

현대의 스마트폰 및 태블릿pc등을 가능하게 만든 집적 기술 중의 하나는 3차원 집적 회로(3D-IC)와 같은 패키징 기술이다. 이러한 첨단 3차원 집적 기술은 메모리집적을 통한 대용량 메모리 모듈 개발뿐만 아니라, 메모리와 프로세서의 집적, high-end FPGA, Back side imaging (BSI) 센서 모듈, MEMS 센서와 ASIC 집적, High Bright (HB) LED 모듈 등에 적용되고 있다. 3D-IC의 3차원 모듈 제작 시에는 기존에 발생하지 않았던 여러 가지 파괴 모드들이 발생하고 있는데 Thermal/Photonic Emission 장비 등 기존의 2차원 결함분리 (Fault Isolation) 기술로는 첨단의 3차원 적층 제품들에서 발생하는 불량을 비파괴적으로 혹은 3차원적으로 분리하는 것이 불가능하므로, 비파괴 3차원 결함 분리 기술은 향후 선행 제품 적기 개발에 매우 필수적인 기술이다. 본 연구는 3D-IC 반도체의 비파괴적 내부결함 검사를 위하여 가시광선-근적외선 대역(351nm~1770nm)의 InGaAs (Indium Galium Arsenide) 계열 영상검출기 (imaging detector)를 사용하여 분광 시스템 광학 설계를 통한 초분광 영상 기반 검출 모듈을 제작하였다. 제작된 초분광 영상 기반 검출 모듈을 이용하여 구리 회로 위에 실리콘 웨이퍼가 3단 적층 된 반도체 더미 샘플의 초분광 영상을 촬영하였으며, 촬영된 초분광 영상에 대하여 Chemometrics model 기반의 분석기술을 적용하여 실리콘 웨이퍼 내부의 집적 구조에 대한 검사가 가능함을 확인하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.271-277
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• 2004

A Si(Silicon) MEMS(Micro Electro Mechanical System) package using a doped lossy Si carrier for CPW(Coplanar Waveguide) MMICs(Microwave and Millimeter-wave Integrated Circuits) is proposed in order to reduce parasitic problems of leakage, coupling and resonance. The proposed chip-carrier scheme is verified by fabricating and measuring a GaAs CPW on the two types of carriers(conductor-back metal, doped lossy Si) in the frequency from 0.5 to 40 ㎓. The proposed MEMS package using the lightly doped lossy(15 Ω$.$cm) Si chip-carrier and the HRS(High Resistivity Silicon, 15 ㏀$.$cm) shows the optimized loss and parasitic problems-free since the doped lossy Si-carrier effectively absorbs and suppresses the resonant leakage. The Si MEMS package for CPW MMICs has an insertion loss of only - 2.0 ㏈ and a power loss of - 7.5 ㏈ at 40 ㎓.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.1
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• pp.36-39
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• 2024

As interest in power semiconductors is growing recently, research on device design and application using light energy gap materials such as SiC and GaN is being actively conducted. Because AlN single crystals have a larger energy gap than the above mentioned materials, research on high-power devices is also in progress, but commercialized wafers have not yet been reported, so research is needed. In this study, we applied the HVPE (Hydride vapor phase epitaxy) method to produce AlN single crystals and attempted to obtain bulk single crystals using our own manufacturing equipment. To this end, we would like to report the results of securing the growth conditions for single crystals. we would like to report on the change in the shape of the grown crystal according to the change in temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.81-81
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• 2009

반도체 산업의 중심 소재인 실리콘(Si)은 사용 목적과 환경에 따라 물성적 한계가 표출되기 시작했다. 그래서 각각의 목적에 맞는 재료의 개발이 필요하다는 것을 인식하게 되었다. SiC wafer는 큰 band gap energy와 고온 안정성, 캐리어의 높은 드리프트 속도 그리고 p-n 접합이 용이하다. 또한 소재 자체가 화학적으로 안정하고 $500\sim600^{\circ}C$에서 소자 제조 시 고온공정이 가능하며, 실리콘이나 GaAs에 비해 고출력을 낼 수 있는 재료이다. 반도체 소자로 이용하기 위한 wafer 가공 공정에 있어 물리적 힘에 의한 stress를 많이 받아 wafer가 휘는 현상이 생긴다. 반도체 소자의 기본이 되는 wafer가 휨 현상을 일으키면 wafer 위에 소자가 올라갈 경우 소자의 불균일성 때문에 반도체의 물성에 나쁜 영향을 미치게 된다. 그래서 반도체 소자의 기본이 되는 wafer의 휨 현상 개선이 중요하다. 본 연구에서는 산화로에서 Ar 분위기에서 압력 760torr, 온도 $1100^{\circ}C$ 부근에서의 조건으로 진행을 하여 wafer의 Flatness Tester(FT-900, NIDEK) 장비로 SORI, BOW, GBIR 값의 변화에 초점을 맞추었다. SiC 단결정을 sawing후 가공 전 wafer를 열처리하여 가공을 진행하는 것과 열처리 하지 않은 wafer의 SORI, BOW, GBIR 값 비교, 그리고 lapping, grinding, polishing 등의 가공 진행 중간 중간에 열처리를 하여 진행하는 것과 가공 진행 중간 중간에 열처리를 하지 않고 진행한 wafer의 SORI, BOW, GBIR 값의 비교를 통해 wafer의 휨 현상 개성에 관해 알아본다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.5
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• pp.218-223
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• 2001

The chemical-mechanical polishing process was carried out for 2"-dia. sapphire wafer grown by horizontalBridgman method on the urethane lapping pad with the silica sol. The polished wafer shows the full-width at halfmaximum of 200~400 arcsec in double-crystal X-ray diffraction, indicating that the slicing, grinding and lapping processes before the polishing process affected the crystalline structural property of the wafer surface by the mechanical residual stress. For the inclusion of surface treatments after chemical-mechanical polishing such as the thermal annealing at the temperature of $1,200^{\circ}C$for 4 hrs. and chemical etching, the crystalline quality was sigdicantly enhanced with the reduced full-width at half maximum up to 8.3 arcsec.arcsec.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.5
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• pp.247-253
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• 2003

In this study, a numerical analysis of the deposition of gallium arsenide from TMGa and arsine in a horizontal MOCVD reactor is performed to investigate the effect of inlet diffuser shape of reactor on the flow and deposition characteristics. The effects of two geometric parameters (diffuser angle, diffuser shape) on the growth rate, growth rate uniformity, flow uniformity and pressure loss are presented. As a results, it is found that the optimum linear diffuser angle is in the range of $50^{\circ}$∼$55^{\circ}$ and parabolic diffuser in the range of $40^{\circ}$∼$45^{\circ}$ from the viewpoint of growth rate uniformity, flow uniformity and average growth rate. It is also found that variation of diffuser angle has greater impact on growth rate uniformity than average growth rate particularly in parabolic diffuser.