• Ecology and Resilient Infrastructure
• /
• v.5 no.4
• /
• pp.276-284
• /
• 2018

In order to analyze sediment transport characteristics of knickpoint migration, sediment transport length, and sediment transport weight through the under-flow type vertical lift gate, the hydraulic model experiment and dimensional analysis were performed. The correlations between Froude number and sediment transport characteristics were schematized. The multiple regression formulae for sediment transport characteristics with non-dimensional parameters were suggested. The determination coefficients of multiple regression equations appeared high as 0.618 for knickpoint migration, 0.632 for sediment transport length, and 0.866 for sediment transport weight. In order to evaluate the applicability of the developed hydraulic characteristic equations, 95% prediction interval analysis was conducted on the measured and the calculated by multiple regression equations, and it was determined that NSE (Nash-Sutcliffe Efficiency), RMSE (root mean square), and MAPE (mean absolute percentage error) are appropriate, for the accuracy analysis related to the prediction on sediment transport characteristics of kickpoint migration, sediment transport length and weight.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.180-184
• /
• 2018

Gallium oxide ($Ga_2O_3$) and silicon carbide (SiC) are the material with the wide band gap ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV). These electronic properties allow high blocking voltage. In this work, we investigated the characteristic of $Ga_2O_3$ and 4H-SiC vertical depletion-mode metal-oxide-semiconductor field-effect transistors. We demonstrated that the blocking voltage and on-resistance of vertical DMOSFET is dependent with structure. The structure of $Ga_2O_3$ and 4H-SiC vertical DMOSFET was designed by using a 2-dimensional device simulation (ATLAS, Silvaco Inc.). As a result, 4H-SiC and $Ga_2O_3$ vertical DMOSFET have similar blocking voltage ($Ga_2O_3-1380V$, SiC-1420 V) and then when gate voltage is low, $Ga_2O_3-DMOSFET$ has lower on-resistance than 4H-SiC-DMOSFET, however, when gate voltage is high, 4H-SiC-DMOSFET has lower on-resistance than $Ga_2O_3-DMOSFET$. Therefore, we concluded that the material of power device should be considered by the gate voltage.

• Journal of Navigation and Port Research
• /
• v.42 no.6
• /
• pp.446-452
• /
• 2018

A traffic route is an area associated with high risk for accidents due to the flow of heavy traffic. Despite this concern, most studies related to traffic focus solely on traffic distribution. Therefore, there is a need for studies investigating the characteristics of ships' routes and traffic patterns. In this study, an investigation was carried out to analyze the traffic distribution and pattern in 3 major traffic routes for 3 days. For the purpose of the study, based on the prevailing traffic conditions, the route was divided into 10 gate lines. The ships passing through the lines were also classified into either small, medium and large. ND-K-S (normal distribution, kurtosis, and skewness) test was carried out for the traffic distribution at each gate line based on the information analyzed on each traffic route. The analysis of the results obtained from the ND test showed that large vessels have normal distribution, medium sized vessels have satisfied normal distribution in one-way route only while small sized vessels do not have normal distribution. According to the result obtained from the K-S test, normal traffic pattern shows a significant difference between two-way route and one-way route. Results obtained from the K test result shows that in the case of one-way route, vessels have a traffic pattern using a wide range on traffic route. Further analysis shows that vessels concentrate on one side of route in case of two-way route. Results obtained from the S test show that, in case of one-way route, vessels have a normal traffic pattern according to center line. However, analysis pf the results shows that vessels are shifted to the right side of route in case of two-way route. Despite these findings, it should be noted that this study was carried out in only 3 ports, therefore there is need for investigation to be carried out in various routes and conditions in future studies.

• Korean Journal of Heritage: History & Science
• /
• v.51 no.3
• /
• pp.72-87
• /
• 2018

This study highlights a drainage gate and a ditch, which existed around the whole area of the western shore of Wolji Pond(月池) and focuses on a possible connection between the drainage facility on the western shore and the historical drainage system of Wolji Pond. Specifically, it primarily considered locations and the form of a drainage gate, the relationship between northwestern ditch of Wolji Pond and the drainage gate, and the establishment period and the character of the drainage facility on the western shore. The drainage gate found in excavation in 1975 is determined as the same facility as Surakgu(水落口) recorded on an actual measurement drawing, 1922. Therefore, it is highly probable that there were already the drainage facility in the western shore of Wolji Pond before the 1920s. The drainage gate constructed by processing rectangular stones has four drainage holes for controlling water level. The way of the drainage through the drainage holes is the same as that of the northern shore of Wolji Pond. From a cadastral map drawn in 1913, it is found that the ditch existed in northwest of Wolji Pond. The ditch was proximate to the drainage gate and shared the same axes. Hence, the ditch and the drainage gate are determined as a organic facility connected to the drainage system of Wolji Pond. In particular, the ditch existed in northwest of Wolji Pond is the basis for judging that the drainage facility in the western shore were established before the 1910s. Water flowed in through drainage holes of the drainage gate is drained into the northwest of Wolji Pond, through the ditch. The establishment period and the intention of the drainage facility on the western shore can be interpreted in two aspects. First, they might be 'a agricultural irrigation facility in the Joseon era', given that Wolji Pond was recorded as a agricultural reservoir, and that the whole northwestern area of Wolji Pond was used as farm land areas. Second, they might be 'a drainage facility for controlling the water level in creating Wolji Pond', given that the drainage gate was annexed to the lower shore forming the waterline of Wolji Pond, and that the hight of drainage holes on top of the drainage gate was similar to the full water level of Wolji Pond. Considering the related grounds and circumstance, the latter possibility is high.

• Annual Conference on Human and Language Technology
• /
• 2018.10a
• /
• pp.281-284
• /
• 2018

본 논문에서는 machine reading 분야에서 기존의 long short-term memory (LSTM) 모델이 가지는 문제점을 해결하는 새로운 네트워크를 제안하고자 한다. 기존의 LSTM 모델은 크게 두가지 제한점을 가지는데, 그 중 첫째는 forget gate로 인해 잊혀진 중요한 문맥 정보들이 복원될 수 있는 방법이 없다는 것이다. 자연어에서 과거의 문맥 정보에 따라 현재의 단어의 의미가 크게 좌지우지될 수 있으므로 올바른 문장의 이해를 위해 필요한 과거 문맥의 정보 유지는 필수적이다. 또 다른 문제는 자연어는 그 자체로 단어들 간의 복잡한 구조를 통해 문장이 이루어지는 반면 기존의 시계열 모델들은 단어들 간의 관계를 추론할 수 있는 직접적인 방법을 가지고 있지 않다는 것이다. 본 논문에서는 최근 딥 러닝 분야에서 널리 쓰이는 attention mechanism과 본 논문이 제안하는 restore gate를 결합한 네트워크를 통해 상기 문제를 해결하고자 한다. 본 논문의 실험에서는 기존의 다른 시계열 모델들과 비교를 통해 제안한 모델의 우수성을 확인하였다.

• Journal of Korea Water Resources Association
• /
• v.51 no.7
• /
• pp.555-564
• /
• 2018

The detention reservoir is a hydraulic structure that constructs a levee on the inland of river and sets up side weir in a section of the levee, and this facility stores a part of the flood volume in case of a flood event over a certain scale. In order to optimize the operation of detention reservoir, it is necessary to review the linkage with existing facilities in the river. In this study, the effect of water level reduction and the flow distribution was analyzed according to the location of the side weir in the detention reservoir considering the run-of-the-river gate. Two radial gates were installed in the experimental channel, and the water level in channel and the overflow of weir were measured by moving the location of the side weir upstream from the gate. As a results of experiment, it was confirmed that the water level reduction is more remarkable as the location of the side weir was closer to the gate, and the effect of flow distribution is not greatly changed. When two or more side weirs were operated, it is confirmed that the sufficient storage space was secured and the water level reduction effect with the location of the side weir is not large. In addition, the water level reduction rate according to the location of the side weir was estimated by empirical formula and it is provided as basic data that can be used in the planning of the detention reservoir.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.448-449
• /
• 2018

최근, WBG 반도체 소자에 대한 연구가 활발히 진행됨에 따라 고속 스위칭으로부터 발생되는 문제점들을 해결하기 위한 여러 방안들이 제시되고 있다. WBG 반도체 소자의 안정적인 고속 스위칭을 실현하기 위해서는 게이트 드라이버 내에 존재하는 기생 인덕턴스를 최소화하는 것이 가장 중요하다. 본 논문에서는 layout의 최적화 설계를 통해 GaN FET 구동용 게이트 드라이버 내의 기생 인덕턴스를 최소화할 수 있는 방안을 제시하고 설계를 통해 만들어진 게이트 드라이버를 실험을 통해 스위칭 특성을 분석하였다.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.21 no.5
• /
• pp.684-696
• /
• 2018

The mission in missile systems can be conducted with multiple phases according to the characteristics of the systems and the targets. The safeguarded multi-phase mission includes a safeguarded phase before launch for considering the safety of operators in unexpected squib activation. However, the safeguard function should be disabled after launch to complete the mission. Therefore, the squib system needs to be selectively activated according to the phases. This paper presents a selective squib activation and check circuit design for safeguarded multi-phase missions in missile systems. The presented circuit design was implemented with various electronic components including a field-programmable gate array(FPGA). Its functions and performance were validated by both many ground tests and several flight tests.

• Journal of Power Electronics
• /
• v.18 no.4
• /
• pp.1037-1050
• /
• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of Power Electronics
• /
• v.18 no.4
• /
• pp.985-996
• /
• 2018

The implementation and performance evaluation of an interleaved boundary conduction mode (BCM) boost power factor correction (PFC) converter is presented in this paper by employing three wide band-gap switching devices: a super junction silicon (Si) MOSFET, a silicon carbide (SiC) MOSFET and a gallium nitride (GaN) high electron mobility transistor (HEMT). The practical considerations for adopting wide band-gap switching devices to BCM boost PFC converters are also addressed. These considerations include the gate drive circuit design and the PCB layout technique for the reliable and efficient operation of a GaN HEMT. In this paper it will be shown that the GaN HEMT exhibits the superior switching characteristics and pronounces its merits at high-frequency operations. The efficiency improvement with the GaN HEMT and its application potentials for high power density/low profile BCM boost PFC converters are demonstrated.