• Transactions of Materials Processing
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• v.17 no.6
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• pp.443-448
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• 2008

Fiber reinforced injection molded parts are widely used in recent years because of their improved properties of materials such as specific stiffness, specific strength, and specific toughness. The demand for products with high precision is increasing and it is important to minimize the warpage of the products. The warpage of short-fiber reinforced product is caused by anisotropy induced by fiber orientation as well as the residual stresses induced during the molding process. In order to reduce the warpage of the part, it is important to achieve successful mold design, processing control, and part design. In the present study, the design of gating system, molding condition, and part structure were carried out and verified with numerical analysis using a commercial CAE code Moldflow. The numbers and locations of gates were iteratively determined, and the molding conditions which can decrease the warpage of the part were investigated. Finally, slight structural modification of the part was conducted to reduce the locally concentrated warpage.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.305-309
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• 2005

A computer code was developed to simulate all three stages of the injection molding process ? filling, packing and cooling by finite element method. The constitutive equation used here was compressible Leonov model. The PVT relationship was assumed to follow the Tait equation. The flow-induced birefringence was related to the calculated flow stresses through the linear stress-optical law. Based on the simulation, the Taguchi method was used to investigate the influences of injection molding conditions on the birefringence of a center gate disk. In addition, the optimal processing conditions were selected to minimize the birefringence and the birefringence difference along the positions of the disk.

• Journal of The Korean Society of Agricultural Engineers
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• v.51 no.6
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• pp.53-62
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• 2009

The EFDC (Environmental Fluid Dynamics Code), a numerical model for simulating three-dimensional (3D) flow, transport, and biogeochemical processes in surface water systems including rivers, reservoirs, and estuaries, was applied to assess the effect of sea water and fresh water exchange rates ($Q_e$) on the mixing characteristics of a conservative pollutant (tracer) induced from upstreams and salinity in Saemangeum Lake, Korea. The lake has been closed by a 33 km estuary embankment since last April of 2006, and now seawater enters the lake partially through two sluice gates (Sinsi and Garyuk), which is driving the changes of hydrodynamic and water quality properties of the lake. The EFDC was constructed and calibrated with surveyed bathymetry data and field data including water level, temperature, and salinity in 2008. The model showed good agreement with the field data and adequately replicated the spatial and temporal variations of the variables. The validated model was applied to simulated the tracer and salinity with two different gate operation scenarios: RUN-1 and RUN-2. RUN-1 is the case of real operation condition ($Q_e=25,000,000\;m^3$) of 2008, while RUN-2 assumed full open of Sinsi gate to increase $Q_e$ by $120,000,000\;m^3$. Statistical analysis of the simulation results indicate that mixing characteristics of pollutants from upstream can be significantly affected by the amount of $Q_e$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.73-79
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• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.147-156
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• 2004

This paper presents an implementation and performance analysis of an access channel decoder which exploits a diversity gain due to the independent magnitude of received signals energy at each of antenna elements of a smart antenna BTS (Base-station Transceiver Subsystem) operating in CDMA2000 1X signal environment. Proposed access channel decoder consists of a searcher supporting 4 fingers, Walsh demodulator, and demodulator controller. They have been implemented with 5 of 1 million-gate FPGA's (Field Programmable Gate Array) Altera's APEX EP20K1000EBC652 and TMS320C6203 DSP (digital signal processing). The objective of the proposed access channel decoders is to enhance the data retrieval at co]1-site during the access period, for which the optimal weight vector of the smart antenna BTS is not available. Through experimental tests, we confirmed that the proposed access channel decoder exploitng the diversity technique outperforms the conventional one, which is based on a single antenna channel, in terms of detection probability of access probe, access channel failure probability, and $E_{b/}$ $N_{o}$ in Walsh demodulator.r.r.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.