• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.244-250
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• 1994

This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

• Journal of Ocean Engineering and Technology
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• v.5 no.1
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• pp.64-70
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• 1991

The design theory of roller gate has been systematized laying more emphasis on practical formulas than theoretical ones and the design procedure of the existing gate facilites is reviewed and analyaed on economical viewpoint and safety factor. The design theory of timoshenko, the thechnical standards for hydraulic gate and penstock of Japan, and the design standards for waterworks structures of Germany are applied to the study of optimal design of a gate leaf. In this study, gate leaf which is now being operated for water control at the seadike, estuary dam and reservoir dam are adopted as a mode, and a new design method by the computer is proposed through the variation of design elements within practical ranges. As a result, safety factor and economical design can be made by using T-beams to the horizontal and vertical beam of the gate leaf instead of H-beams used in the existing seadike roller gate at Asan, and total weight of gate leaf is reduced by the present optimization.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.261-263
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• 2002

CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

• Journal of Navigation and Port Research
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• v.30 no.4
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• pp.277-283
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• 2006

It is a world trend to construct large terminal and develop automated container terminal to attract Super Post-Panamax and provide service which is based on differentiation. In fact, there is insufficient research for automatization of terminal gate since the automatization of current constructed container terminal is only focused on increasing productivity and unmanned system through the automatization of quay, yard, etc. In this paper, we have investigated advantage/disadvantage of existing gate operation systems and compared each gate operation system in the aspect of raising terminal image and the productivity. For the specific study, we have used data from actual terminal gate operation and RFID model business sponsored by MOMAF (Ministry of Maritime Affairs and Fisheries). As a result, this paper carried out an efficient gate operation system and it has been expected that it will be performed as groundwork of automated gate operation system which is for design of container terminal and improvement of gate operation system.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.12-15
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• 2022

In this study, we studied the effects of transfer gate on the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector. The GBT MOSFET-type photodetector has high sensitivity owing to the amplifying characteristic of the photocurrent generated by light. The transfer gate controls the flow of photocurrent by controlling the barrier to holes, thereby varying the sensitivity of the photodetector. The presented GBT MOSFET-type photodetector using a built-in transfer gate was designed and fabricated via a 0.18-㎛ standard complementary metal-oxide-semiconductor (CMOS) process. Using a laser diode, the photocurrent was measured according to the wavelength of the incident light by adjusting the voltage of the transfer gate. Variable sensitivity of the presented GBT MOSFET-type photodetector was experimentally confirmed by adjusting the transfer gate voltage in the range of 405 nm to 980 nm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.498-501
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator. DG MOSFET have the main gate length of nm and the side gate length of 70nm. Then, we have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nino scale.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Journal of IKEEE
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• v.25 no.2
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• pp.381-387
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• 2021

As Head-Mounted Displays(HMDs), which are mainly used to maximize realism in games and videos, have experienced increased demand and expanded scope of use in education and training, there is growing interest in methods to enhance the performance of conventional HMDs. In this study, a methodology to utilize Carbon NanoTubes(CNTs) to improve the performance of gate drivers that send control signals to each pixel circuit of the HMD is discussed. This paper proposes a new circuit design method that replaces the transistors constituting the buffer part of the conventional gate driver with transistors incorporating CNTs and compare the performance of the suggested gate drive with that of a gate driver comprising only conventional transistors via simulations. According to the simulation results, by including CNTs in the gate driver, the output voltage can be increased by approximately 0.3V compared to the conventional gate driver high voltage(1.1V) at a speed of 12.5 GHz and the gate width also can be reduced by up to 20 times.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.