• Title/Summary/Keyword: GATE

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Model Tests Study on Flow-induced Vibrationof Tainter Gate in Estuary Sulices(Ⅱ)- Flow from the Gate Inside to the Gate Outside - (배수갑문 테인터 게이트(Tainter Gate)의 진동현상에 관한 모형실험(Ⅱ)- 문비 안에서 밖으로의 흐름 -)

  • Lee , Seong-Haeng;Woo , Sang-Ik
    • Journal of The Korean Society of Agricultural Engineers
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    • v.46 no.2
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    • pp.41-47
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    • 2004
  • A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1:25 is made of acryl panel dimensioned 0.66 m in width, 0.5 m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. In the flow from the gate inside to the gate outside, the amplitudes of the vibration are measured under the different gate opening and downstream water level conditions. Also revised gate models with 20 mm bottom width are tested under the different gate openings and water levels. The results are analyzed to study the characteristics of the Tainter gate vibration in the sea ward flow. These test results are assessed in comparison with the results in the lake ward flow, as a result, presents the dynamic characteristics of the Tainter gate and a basic data for the guide manuals of gate management.

MIC-TFT의 Single, Dual Gate의 전기적 특성

  • Kim, Jae-Won;Han, Jae-Seong;Choe, Byeong-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.135-135
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    • 2009
  • In this work we compared the electrical characteristic of single gate and dual gate in MIC-TFT. We fabricated p-channel TFTs based on MIC structure. In mobility, dual gate ($61.35cm^2/Vsec$) got a higher value than single gate ($55.96cm^2/Vsec$). In $I_{on}/I_{off}$ dual gate ($6.94{\times}10^6$) got a higher value than single gate ($1.72{\times}10^6$) too. In $I_{off}$, dual gate got a lower value than single gate. Therefore, dual gate is good and less power consumption than single gate.

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A Study on the Formation of Gate Mark in Injection Molding (사출성형에서 Gate Mark의 형성에 관한 연구)

  • Kim, J.M.;Kim, D.W.;Hwang, S.J.;Lyu, M.Y.
    • Transactions of Materials Processing
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    • v.15 no.8 s.89
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    • pp.628-632
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    • 2006
  • The gate mark in injection molded part is a kind of surface defects. The formation of gate mark has been investigated in this study. SEM photographs and surface roughness have been examined to study gate mark. The specimens were molded for various injection conditions, such as injection temperature, mold temperature, and injection speed. Gate diameter and mold surface condition were also molding variables. Gate marks were reduced as injection speed and mold temperature increased. Gate diameter and injection temperature did not affect the gate marks. No etching of mold surface showed no gate marks for any molding conditions.

Trench Power MOSFET using Separate Gate Technique for Reducing Gate Charge (Gate 전하를 감소시키기 위해 Separate Gate Technique을 이용한 Trench Power MOSFET)

  • Cho, Doohyung;Kim, Kwangsoo
    • Journal of IKEEE
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    • v.16 no.4
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    • pp.283-289
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    • 2012
  • In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

Model Tests Study on Flow-induced Vibration of Truss Type Lift Gate (트러스형 리프트 게이트의 진동현상에 관한 모형실험)

  • Lee, Seong-Haeng;Kim, Ha-Jip;Park, Young-Jin;Hahm, Hyung-Gil;Kong, Bo-Sung
    • Journal of The Korean Society of Agricultural Engineers
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    • v.53 no.3
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    • pp.35-41
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    • 2011
  • A model test is carried out to investigate the vibration of truss type lift gate in the four major rivers project. The gate model scaled with the ratio of 1 : 25 is made of acryl panel dimensioned 1.6 m in width, 0.28 m in height in the concrete test flume. Firstly natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. The amplitudes of the vibration are measured under the different gate opening and water level conditions. The results are analyzed to study the characteristics of the gate vibration according to the small gate opening, the large gate opening and the overflow conditions. These test results presents a basic data for the guide manuals of gate management and a design method to reduce the gate vibration of truss type lift gate. Finally, the vibration of truss type lift gate are assessed in comparison with those of formerly tainter gate.

A Study Comparison and Analysis of Electrical Characteristics of IGBTs with Variety Gate Structures (다양한 게이트 구조에 따른 IGBT 소자의 전기적 특성 비교 분석 연구)

  • Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.11
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    • pp.681-684
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    • 2016
  • This research was carried out experiments of variety IGBTs for industrial inverter and electric vehicle. The devices for this paper were planar gate IGBT, trench gate IGBT and dual gate IGBT and we designed using same design and process parameters. As a result of experiments, the electrical characteristics of planar gate IGBT were 1,459 V of breakdown voltage, 4.04 V of threshold voltage and 4.7 V of on-state voltage drop. And the electrical characteristics of trench gate IGBT were 1,473 V of breakdown voltage, 4.11 V of threshold voltage and 3.17 V of on-state voltage drop. Lastly, the electrical characteristics of dual gate IGBT were 1,467 V of breakdown voltage, 4.14 V of threshold voltage and 3.08V of on-state voltage drop. We almost knew that the trench gate IGBT was superior to dual gate IGBT in terms of breakdown voltage. On the other hand, the dual gate IGBT was better than the trench gate IGBT in terms of on state voltage drop.

Gate Driving Methods to Compensate Feed-Through Voltage for Large Size, High Quality TFT-LCD (대면적 고화질 TFT-LCD의 Feed-through 전압 보상을 위한 Gate Driving 방법)

  • 정순신;윤영준;박재우;최종선
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.11a
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    • pp.99-102
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    • 1999
  • In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate signal delay, feed-through voltage and image sticking. To improve these problems which are caused by the fried-through voltage, we have evaluated new driving methods to reduce the fled-through voltage. Two level gate-pulse was used for the gate driving of the cst-on-common structure pixels. And two-gate line driving methods with the optimized gate signals were applied for the cst-on-gate structure pixels. These gate driving methods were better feed-through characteristics than conventional simple gate pulse. The evaluation of the suggested driving methods were performed by using a TFT-LCD array simulator PDAST which can simulate the gate, data and pixel voltages of a certain pixel at any time and at any location on a TFT array. The effect of the new driving method was effectively analyzed.

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Design of XOR Gate Based on QCA Universal Gate Using Rotated Cell (회전된 셀을 이용한 QCA 유니버셜 게이트 기반의 XOR 게이트 설계)

  • Lee, Jin-Seong;Jeon, Jun-Cheol
    • Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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    • v.7 no.3
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    • pp.301-310
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    • 2017
  • Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

Experimental fabrication and analysis on the double injection semiconductor switching devices (반도체 DI swiching 소자의 시작과 특성에 관한 실험적 고찰)

  • 성만영;정세진;임경문
    • Electrical & Electronic Materials
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    • v.4 no.2
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    • pp.159-174
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    • 1991
  • 이중주입효과에 의한 고내압 반도체 스위칭소자의 설계 제작에 촛점을 맞추어 Injection Gate구조와 MOS Gate 구조로 시료소자를 제작해 그 특성을 검토하고 Electrical Switching 및 Oxide막에서의 Breakdown현상에 의한 문제점을 해결해 보고자 Optical Gate구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 및 MOS Gate 구조(Planar type, V-Groove type, Injection Gate mode, Optical Gate mode)로 설계제작된 소자와 특성을 비교 분석하였다.

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Gate Tunneling Current and QuantumEffects in Deep Scaled MOSFETs

  • Choi, Chang-Hoon;Dutton, Robert W.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.1
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    • pp.27-31
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    • 2004
  • Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.