• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• 센서학회지
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• 제6권3호
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• pp.221-227
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• 1997

Pd/NiCr 게이트 MISFET 센서는 변압기 절연유중 용존수소를 감지하기 위해 제조되었다. 센서의 안정성과 고농도 감지성의 향상을 위해 Pd/NiCr 2중 촉매 금속 게이트가 사용되었다. 수소유입에 의한 게이트 전압의 드리프트를 줄이기 위해, 2개의 FET 게이트 절연층을 실리콘 산화막과 실리콘 질화막의 2중 구조로 하였다. Pd/NiCr 게이트 MISFET 센서의 수소 감응 감도는 Pd/Pt 게이트 MISFET 센서의 감도에 비해 약 0.5배이나, 안정성이 좋고, 1000 ppm까지의 고농도까지 측정할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• 한국전기전자재료학회논문지
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• 제22권12호
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• pp.1009-1013
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• 2009

In this study, we have been synthesized the dielectric layer using pure organic and organic-inorganic hybrid precursor on flexible substrate for improving of the organic thin film transistors (OTFTs) and, design and fabrication of organic thin-film transistors (OTFTs) using small-molecule organic semiconductors with pentacene as the active layer with record device performance. In this work OTFT test structures fabricated on polymerized substrates were utilized to provide a convenient substrate, gate contact, and gate insulator for the processing and characterization of organic materials and their transistors. By an adhesion development between gate metal and PI substrate, a PI film was treated using $O_2$ and $N_2$ gas. The best peel strength of PI film is 109.07 gf/mm. Also, we have studied the electric characteristics of pentacene field-effect transistors with the polymer gate-dielectrics such as cyclohexane and hybrid (cyclohexane+TEOS). The transistors with cyclohexane gate-dielectric has higher field-effect mobility, $\mu_{FET}=0.84\;cm^2/v_s$, and smaller threshold voltage, $V_T=-6.8\;V$, compared with the transistor with hybrid gate-dielectric.

• 한국농공학회논문집
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• 제58권6호
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• pp.31-38
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• 2016

The purpose of this study was to assess nonpoint sources (NPS) pollution affected by liquid manure and regulating gate in a small agricultural watershed. The study area, which is a wide plain farmland, was operating by the Buyong regulating gate in order to maintain irrigation water level during irrigation period. Consequentially, runoff only occurs through the gate at each event in rainy season for avoiding farmland inundation. In addition, the usage ratio of liquid manure in the study area has been increased greatly since 2014. Discharge loads at the Hwaingsan bridge subwatershed were 1.2 times for T-N, 4-10 times for T-P, and 3-8 times for TOC compared with the Soyang watershed (control) during study period. The reason was that NPS pollutants from upper Gpeun and Sangri bridge subwatersheds, which are widely spraying with livestock liquid manure, were stack at this subwaterehd because of regulating gate in non-rainy seasons. A number of agricultural watersheds in Saemangeum watershed are affected by regulating gate and vigorous livestock activities so that substantial management schemes under controling regulating gate are needed for minimizing livestock related NPS.

• 한국진공학회지
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• 제5권2호
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.10-17
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• 2009

Double-Gate MOSFET 구조를 사용한 Nano-Electro-Mechanical MOSFET (NEMFET)는 게이트 길이가 짧아지면서 나타나는 단채널 현상을 효과적으로 제어하는 새로운 구조의 차세대 소자이다. 특히 공핍형 Double-gate NEMFET (Dep-DGNEMFET)은 차단 상태에서 얇은 산화막을 가지므로 subthreshold 전류가 효과적으로 제어된다. 이러한 Dep-DGNEMFET 특성에 대한 해석적 수식을 유도하고 소자 구조가 변화하는 경우의 특성 변화를 분석하였다. 또한 ITRS (International Technology Roadmap for Semiconductors) 전류 기준값을 만족시키기 위하여 Dep-DGNEMFET 소자 구조를 최적화 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.9-12
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• 2004

This paper investigated the stability of Ta-Mo alloy on thin gate dielectric. Ta-Mo alloy was deposited by using co-sputtering process after thermal growing of 3.4nm and 4.2nm silicon dioxide. When the sputtering power of Ta and Mo were 100W and 70W, respectively, the suitable work function for NMOS gate electrode, 4.2eV, could obtain. To prove interface thermal stability of thin film gate dielectric and Ta-Mo alloy, rapid thermal annealing was performed at $600^{\circ}C$ and $700^{\circ}C$ for 10sec in Ar ambient. The results of interface reaction were surveyed by change of silicon dioxide thickness and work function after annealing process. Also, the reliability of alloy gate and gate dielectric could be confirmed by quantity of leakage current. Ta-Mo alloy was showed low sheet resistance and thermal stability, namely, little change of gate dielectric and work function, after $700^{\circ}C$ annealing process.