• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• ETRI Journal
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• v.11 no.4
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• pp.22-36
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• 1989

In this paper, a design and implementation of an efficient protocol verification system named LOVE has been described. The LOVE has been developed specifically for LOTOS. It performs not only protocol syntax validation (PSV) but also protocol functional verification(PFV). The PSV is a test to check if a protocol is free from protocol syntax errors such as deadlocks and livelocks. The PFV confirms whether or not a protocol achieves its functional objectives. For the PSV, the reachability analysis is employed, and the observational equivalence test is used for the PFV. For protocol verification using the LOVE, a schematic protocol verification methodology has been outlined.

• The Journal of Korean Association of Computer Education
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• v.9 no.4
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• pp.43-54
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• 2006

In general, user requirements in web-based learning systems are divided into functional and non-functional requirements. Developers are responsible for the verification of quality related requirements, which is known to be difficult to perform. This paper suggests a verification method that can be applied in the area where the conformance of implementation for non-functional requirements is required. The paper performs tests for non-functional requirements by using the information extracted from quality related features that have imposed constraints on design activities.

• Nuclear Engineering and Technology
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• v.46 no.3
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• pp.381-386
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• 2014

A highly reliable safety class controller for NPPs (Nuclear Power Plants) is mandatory as even a minor malfunction can lead to disastrous consequences for people, the environment or the facility. In order to enhance the reliability of a safety class digital controller for NPPs, we employed a diversity approach, in which a PLC-type controller and a PLD-type controller are to be operated in parallel. We built and used structured testbenches based on the classes supported by UVM for functional verification of the PLD-type controller designed for NPPs. We incorporated a UVM register model into the testbenches in order to increase the controllability and the observability of the DUT(Device Under Test). With the increased testability, we could easily verify the datapaths between I/O ports and the register sets of the DUT, otherwise we had to perform black box tests for the datapaths, which is very cumbersome and time consuming. We were also able to perform constrained random verification very easily and systematically. From the study, we confirmed the various advantages of using the UVM register model in verification such as scalability, reusability and interoperability, and set some design guidelines for verification of the NPP controllers.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.219-230
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• 2023

With the development of autonomous driving technology, as the use of software in vehicles increases, the complexity of the system increases and the difficulty of development increases. Developments that meet ISO 26262 must be carried out to reduce the malfunctions that may occur in vehicles where the system is becoming more complex. ISO 26262 for the functional safety of the vehicle industry proposes to consider functional safety from the design stage to all stages of development. Specifically at the software level, the requirements to be complied with during development and the requirements to be complied with during verification are defined. However, it is not clearly expressed about specific design methods or development methods, and it is necessary to supplement development guidelines. The importance of analysis and verification of requirements is increasing due to the development of technology and the increase of system complexity. The vehicle industry must carry out developments that meet functional safety requirements while carrying out various development activities. We propose a process that reflects the perspective of system engineering to meet the smooth application and developmentrequirements of ISO 26262. In addition, the safety analysis/verification FMEA processforthe safety of the proposed ISO 26262 function was conducted based on the FCAS (Forward Collision Avoidance Assist System) function applied to autonomous vehicles and the results were confirmed. In addition, the safety analysis/verification FMEA process for the safety of the proposed ISO 26262 function was conducted based on the FCAS (Forward Collision Avoidance Assist System) function applied to the advanced driver assistance system and the results were confirmed.

• Asian Pacific Journal of Cancer Prevention
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• v.13 no.3
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• pp.985-989
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• 2012

Objective: To make sure the feasibility with $^{18F}FDG$ PET/CT to guided dynamic intensity-modulated radiation therapy (IMRT) for nasopharyngeal carcinoma patients, by dosimetric verification before treatment. Methods: Chose 11 patients in III~IVA nasopharyngeal carcinoma treated with functional image-guided IMRT and absolute and relative dosimetric verification by Varian 23EX LA, ionization chamber, 2DICA of I'mRT Matrixx and IBA detachable phantom. Drawing outline and making treatment plan were by different imaging techniques (CT and $^{18F}FDG$ PET/CT). The dose distributions of the various regional were realized by SMART. Results: The absolute mean errors of interest area were $2.39%{\pm}0.66$ using 0.6cc ice chamber. Results using DTA method, the average relative dose measurements within our protocol (3%, 3 mm) were 87.64% at 300 MU/min in all filed. Conclusions: Dosimetric verification before IMRT is obligatory and necessary. Ionization chamber and 2DICA of I'mRT Matrixx was the effective dosimetric verification tool for primary focal hyper metabolism in functional image-guided dynamic IMRT for nasopharyngeal carcinoma. Our preliminary evidence indicates that functional image-guided dynamic IMRT is feasible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.43-52
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• 2004

This paper proposes an efficient functional verification environment of microprocessor. This verification environment consists of test vector generator part, simulator part, and comparator part. To enhance efficiency of verification, it use a bias random test vector generator. In a part of simulation, retargetable instruction level simulator is used for reference model. This verification environment is excellent to find error which is not detected by general test vector and will become a good guide to find new error type

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• Plant Journal
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• v.13 no.4
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• pp.41-47
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• 2017

This paper is a study on validation model that can verify the arrangement of equipment constituting offshore plant using system engineering approach in offshore plant tender stage. In order to design offshore plant topside maintenance equipment, topside layout verification should be preceded. However, there are many errors in the bidding stage due to the FEED results that are not perfect, the verification can not be performed sufficiently due to the limitation of the bidding period and others reasons. Therefore, we propose a validation model that can effectively verify the equipment layout within a limited condition by simplifying the main process in the system engineering process, which is a multidisciplinary approach, and confirmed through the Functional Deployment Model. Also, we verified the validation model for topside equipment deployment through case studies.