• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.248-248
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• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.60-60
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• 2003

디자인 룰에 의해 Gate Length 가 100nm 이하로 줄어듦에 따라 Gate delay 감소와 Switch speed 향상을 위해 보다 더 큰 drive current 를 요구하게 되었다. 본 연구는 dirve current 를 증가시키기 위해 고안된 Strained Si substrate 를 만들기 위한 SiGe layer 성장에 관한 연구이다. SiGe layer를 성장시킬 때 SiH$_4$ gas와 GeH$_4$ gas를 furnace에 flow시켜 Chemical 반응에 의해 Si Substrate를 성장시키는 LPCVD(low pressure chemical vapor depositio)법을 사용하였고 SIMS와 nanospec을 이용하여 박막 두께 및 Ge concentration을 측정하였고, AFM으로 surface의 roughness를 측정하였다. 본 연구에서 우리는 10,20,30,40%의 Ge concentration을 갖는 10nm 이하의 SiGe layer를 얻기 위하여 l0nm 이하의 fixed 된 두께로 SiGe layer를 성장시킬 때 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$의 gas ratio를 변화시켜 성장시킨 후 Ge 의 concentration과 실제 형성된 두께를 측정하였고, SiGe의 mole fraction의 변화에 따른 surface의 roughness 를 측정하였다. 그 결과 10 nm의 두께에서 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$ 의 gas ratio의 변화와 Ge concentration 과의 의존성을 확인 할 수 있었고, SiGe 의 mole traction이 증가하였을 때 surfcace의 roughness 가 증가함을 알 수 있었다. 이 연구 결과는 strained Si 가 가지고 있는 strained Si 내에서 n-FET 와 P-FET사이의 불균형에 대한 해결과 좀 더 발전된 형태인 fully Depleted Strained Si 제작에 기여할 것으로 보인다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.676-680
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• 2010

In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.1
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• pp.223-228
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• 2017

In this paper, we are proposing an optimal design of wideband pulsed type gamma-ray sensors. These sensors were manufactured based on the design results and after word electrical properties were analyzed. The sensor input parameters were derived on the basis of pulsed gamma-ray spectrum and time-dependent energy rate, and the output current which were derived on the basis of the sensor sensitivity control circuit. Pulsed gamma-ray sensors were designed using the TCAD simulators. The design results show that the optimal Epi layer thickness is 45um with the applied voltage 3.3V and the diameter is 2.0mm. The doping concentrations are as follows : N-type is an Arsenic as $1{\times}10^{19}/cm^3$, P-type is a Boron as $1{\times}10^{19}/cm^3$ and Epi layer is Phosphorus as $3.4{\times}10^{12}/cm^3$. The fabricated sensor was a leakage current, 12pA at voltage -3.3V and fully depleted mode at voltage -5V. A test result of pulsed radiation shows that the sensor gives out the optimal photocurrent.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.35-43
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• 1999

We propose and analyze novel optical thyristor which can be used in free-space optical interconnection(FSOI). Novel optical thyristors are fully depleted optical thyristors(DOTs) using bottom mirror and/or multiple quantum wells (MQW), thereby its switching characteristics can be improved significantly. We obtain switching characteristics using coupled junction model associated with current oriented method. Emission characteristics of the DOT are obtained using thin film characteristic matrix and van Roosbroeck-Shockley relation. Compared to the performance using conventional DOT, the optical switching energy is decreased by a factor of 0.43 and the bit-rate is increased by a factor of 1.61 when the DOT with MQW and bottom mirror is employed for FSOI.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.96-96
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• 2016

나노섬유(nanofiber), 나노선(nanowire), 그리고 나노튜브(nanotube)와 같은 1차원 구조의(one-dimensional structure) 나노재료는 벌크(bulk) 및 박막(film) 재료와는 다르게 물리적, 화학적으로 특이한 성질을 가지고 있으며, 이러한 성질은 나노재료의 구조, 형상, 크기 등에 큰 영향을 받는다. 첫 째, 전기방사(electrospinning) 공정을 이용한 나노섬유의 합성; 용액의 특성, 전기장 세기, 방사시간 등의 변수를 조절하게 되면 방출되는 재료의 형상을 입자 혹은 섬유상의 형태로 얻을 수 있으며, 전기방사를 통해 합성된 나노재료의 소결 온도 및 시간을 달리함으로써 나노입자의 크기를 조절할 수 있다. 또한, 템플레이트 합성법(template synthesis) 및 이중노즐(coaxial nozzle)을 이용해 속이 빈 형태인 중공(hollow) 구조의 나노섬유를 얻을 수 있으며, 전기방사에 사용되는 전구물질에 원하는 금속 및 산화물을 첨가함으로써 복합체(composite) 나노섬유를 얻을 수 있다. 둘 째, VLS(Vapor-Liquid-Solid) 공정을 이용한 나노선의 성장; 온도, 압력, 전구물질의 양, 그리고 시간 등의 변수를 조절하게 되면 원하는 직경 및 길이를 갖는 나노선을 성장시킬 수 있다. 그리고 ALD(Atomic Layer Deposition)를 이용해 나노선에 추가적인 층을 형성함으로써 코어-셀 구조를 형성할 수 있으며, 감마선, UV와 같은 공정을 이용해 귀금속 촉매를 나노선에 기능화 시킬 수도 있다. 코어-셀 구조를 갖는 나노선/나노섬유는 코어 혹은 셀 층의 전자나 홀의 이동을 유발하여 전자공핍층(electron depletion layer) 또는 정공축적층(hole accumulation layer)을 확대 및 축소시켜 센서의 초기저항을 증가시키거나 감소시키는 역할로써 이용되고 있으며, 특히, 셀 층의 두께가 셀 층 재료의 Debye length와 유사한 크기를 갖게 되면, 셀 층은 완전공핍층(fully depleted layer)을 형성해 최대의 감도를 나타낼 수 있다. 본 연구에서는 다양한 제조 공정을 통해 제작될 수 있는 1차원 나노-구조물을 가스센서에 적용하는 사례들을 소개하고, 이러한 가스센서의 감응성능을 향상시키기 위한 방법의 한 가지로 원자층증착법으로 나노선/나노섬유의 표면에 셀층을 형성하여 감응성 향상 메커니즘 및 관련 주요 변수들을 조사하고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2183-2188
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.