• Title/Summary/Keyword: Frequency synthesizer

Search Result 313, Processing Time 0.028 seconds

Design and Implementation of LNA and BPF for RF System in Digital TRS Base Station (I) ; Receiving Part (디지털 TRS 기지국의 RF 시스템 수신부를 위한 저잡음증폭기와 대역통과필터의 설계 및 제작)

  • 구인모;이상설
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.10 no.6
    • /
    • pp.900-909
    • /
    • 1999
  • The receiving part of the RF system for the digital TRS base stations is developed in this paper. Based on the system specifications, the structure of the RF system is accomplished and its block diagram is drawn. The RF system is implemented according to these block diagrams. Subsequently the RF band-pass filter, the low noise amplifier, the automatic level controlled attenuator, the frequency synthesizer and other components for the system are designed and implemented, and a main board to integrate these modules is also manufactured. To lower the noise floor of the system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the RF system and the entire system, the performance tests are accomplished to check the specifications.

  • PDF

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

  • Lee, Jong Mi;Jee, Dong-Woo;Kim, Byungsub;Park, Hong-June;Sim, Jae-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.15 no.3
    • /
    • pp.342-348
    • /
    • 2015
  • This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

Implementation of the VHF EPIRB using the technique of Digital Selective Calling (디지털 선택호출 기술을 이용한 VHF EPIRB의 구현)

  • 유형열;이헌택;황운택;김기문
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.2 no.2
    • /
    • pp.259-266
    • /
    • 1998
  • 406MHz and INMARSAT-E EPIRB facility transmits the distress alerts by the relay of the polar-satellites and INTELSAT, but may cause the probability of delayed transmission because of the orbital period and not compliance with the implementation of GMDSS rules for small ships in A1 area.. Digital Selective Calling forms a critical part of the terrestrial elements of the GMDSS system and ensures the reliability and the efficiency in the system. In this paper, we suggests that new DSC EPIRB in the VHF band to overcome this defect for small ships in A1 area, and analyze the ITU-R recommendations and technical characteristics, design and implement the algorithm of calling sequences, frequency synthesizer for the RF signal and FSK moulation signals.

  • PDF

Two-Stage Ring Oscillator using Phase-Look-Ahead Mehtod and Its Application to High Speed Divider-by-Two Circuit (진상 위상 기법을 이용한 2단 링 구조 발진기 및 고속 나누기 2 회로의 고찰)

  • Hwang, Jong-Tae;Woo, Sung-Hun;Hwang, Myung-Woon;Ryu, Ji-Youl;Cho, Gyu-Hyeong
    • Proceedings of the KIEE Conference
    • /
    • 1999.07g
    • /
    • pp.3181-3183
    • /
    • 1999
  • A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.

  • PDF

CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer (확장성 신뢰성 갖춘 양자 컴퓨터를 위한 CMOS 기반 제어 및 센싱 회로 기술)

  • Jusung Kim;Junghwan Han;Jae-Won Nam;Kunhee Cho
    • Journal of IKEEE
    • /
    • v.27 no.1
    • /
    • pp.12-18
    • /
    • 2023
  • The current circuit technology that individually connects each qubit to a control circuit at room temperature has limitations in achieving scalability and reliability of a quantum computer. With the advent of cryogenic CMOS interconnect electronics, it is expected to dramatically improve the interconnect complexity, system reliability and size, and price. In this paper, we introduce the CMOS integrated sensing and control technology platform overcoming the problems caused by the fragile and sensitive characteristics of qubit.

Nonlinear Speech Production Modeling using Nonlinear Autoregressive Exogenous based on Support Vector Machine (서포트 벡터 머신 기반 비선형 외인성 자귀회귀를 이용한 비선형 조음 모델링)

  • Jang, Seung-Jin;Kim, Hyo-Min;Park, Young-Choel;Choi, Hong-Shik;Yoon, Young Ro
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2007.11a
    • /
    • pp.113-116
    • /
    • 2007
  • In this paper, our proposed Nonlinear Autoregressive Exogenous (NARX) based on Least Square-Support Vector Regression (LS-SVR) is introduced and tested for producing natural sounds. This nonlinear synthesizer perfectly reproduce voiced sounds, and also conserve the naturalness such as jitter and shimmer, compared to LPC does not keep these naturalness. However, the results of some phonation are quite different from the original sounds. These results are assumed that single-band model can not afford to control and decompose the high frequency components. Therefore multi-band model with wavelet filterbank is adopted for substituting single band model. As a results, multi-band model results in improved stability. Finally, nonlinear speech modeling using NARX based on LS-SVR can successfully reconstruct synthesized sounds nearly similar to original voiced sounds.

Implementation of Compressive Receiver with Chirp LO Based on DDS for RFID Signal Detection (DDS 기반의 Chirp LO가 적용된 RFID 신호 탐지용 컴프레시브 수신기의 구현)

  • Jo, Won-Sang;Park, Dong-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.20 no.11
    • /
    • pp.1186-1193
    • /
    • 2009
  • In this paper, we propose DDS(Direct Digital Synthesizer) as a new implementation method of chirp LO(Local Oscillator) for compressive receiver applied for RFID signal detection in UHF band. We designed a receiver whose input frequency range is 908.5~914 MHz, DDL(Dispersive Delay Line) bandwidth is 6 MHz, and dispersion delay time is $13\;{\mu}s$. Chirp LO based on DDS is designed to meet $26\;{\mu}s$ sweep time and 12 MHz bandwidth for complete compressive mechanism. The measured 3 dB pulse width of the compressed signal of the fabricated receiver is 260 ns and the frequency resolution for simultaneous input signals is below 200 kHz. These performances indicate that the proposed chirp LO based on DDS and the compressive receiver is suitable for RFID signal detection in UHF band.

Design of 10.525GHz Self-Oscillating Mixer Using P-Core Voltage Controlled Oscillator (P-코어 VCO를 사용한 10.525GHz 자체발진 혼합기의 설계)

  • Lee, Ju-Heun;Chai, Sang-Hoon
    • The Journal of Korean Institute of Information Technology
    • /
    • v.16 no.11
    • /
    • pp.61-68
    • /
    • 2018
  • This paper describes design of a 10.525 GHz self oscillating mixer semiconductor IC chip combining voltage controlled oscillator and frequency mixer using silicon CMOS technology for Doppler radar applications. The p-core type VCO included in the self oscillating mixer minimizes the noise contained in the transmitted signal. This noise minimization increases the sensing distance and acts in a direction favorable to the reaching distance and the sensitivity of the motion detection sensor. Simulation results for phase noise show that a VCO designed as a P-core has a noise characteristic of -106.008 dBc / Hz at 1 MHz offset and -140.735 dBc / Hz at 25 MHz offset compared to a VCO designed with N-core and NP-core showed excellent noise characteristics. If a self-oscillating mixer is implemented using a p-core designed VCO in this study, a motion sensor with excellent range and reach sensitivity will be produced.

Development of a Multichannel Eddy Current Testing Instrument(II) (다중채널 와전류탐상검사 장치 개발(II))

  • Lee, Hee-Jong;Nam, Min-Woo;Cho, Chan-Hee;Yoo, Hyun-Joo;Kim, In-Chel
    • Journal of the Korean Society for Nondestructive Testing
    • /
    • v.31 no.5
    • /
    • pp.552-559
    • /
    • 2011
  • Recently, the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction phenomenon. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In the previous study, the synthesizer module and the analog module which is essential to the ECT system were primarily developed, and in this study the data acquisition and analysis program were developed. The operation system for this program is based on the Windows 7, and optimized for the Korean users, and the specific feature of this program using setup wizard enables inspector to make a setup easily for acquisition and analysis of ECT data. In this paper, the configuration and functions of eddy current data acquisition and analysis program will be introduced.

Influences and Compensation of Phase Noise and IQ Imbalance in Multiband DFT-S OFDM System for the Spectrum Aggregation (스펙트럼 집성을 위한 멀티 밴드 DFT-S OFDM 시스템에서 직교 불균형과 위상 잡음의 영향 분석 및 보상)

  • Ryu, Sang-Burm;Ryu, Heung-Gyoon;Choi, Jin-Kyu;Kim, Jin-Up
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.21 no.11
    • /
    • pp.1275-1284
    • /
    • 2010
  • 100 MHz bandwidth and 1 Gbit/s data speed are needed in LTE-advanced for the next generation mobile communication system. Therefore, spectrum aggregation method has been studied recently to extend usable frequency bands. Also bandwidth utilization is increased since vacant frequencies are used to communicate. However, transceiver structure requires the digital RF and SDR. Therefore, frequency synthesizer and PA must operate over wide-bandwidth and RF impairments also increases in transceiver. Uplink of LTE advanced uses DFT-S OFDM using plural power amplifier. The effect of ICI increases in frequency domain of receiver due to phase noise and IQ imbalance. In this paper, we analyze influences of ICI in frequency domain of receiver considering phase noise and IQ imbalance in multiband system. Also, we separate phase noise and IQ imbalance effect from channel response in frequency domain of uplink system. And we propose a method to estimate the channel exactly and to compensate IQ imbalance and phase noise. Simulation result shows that the proposed method achieves the 2 dB performance gain of BER=$10^{-4}$.