• Journal of electromagnetic engineering and science
• /
• 제11권3호
• /
• pp.201-206
• /
• 2011

This paper presents a miniaturized epsilon negative (ENG) zeroth-order resonance (ZOR) patch antenna with an improved bandwidth. The miniaturization and the broad bandwidth of the ENG ZOR patch antenna are achieved by using a meandered via and a high permeability substrate instead of a straight via and a dielectric substrate. The use of a meandered via allows miniaturization of the ENG ZOR patch antenna without narrowing the bandwidth. The use of a high permeability substrate allows further miniaturization of the ENG ZOR patch antenna and improvement of the bandwidth. A high permeability substrate consisting of a multi-layered substrate is designed to have a small material loss. The antenna (kr=0.32) has a 10 dB fractional bandwidth of ~1 %, which is 1.74 times as broad as that of an antenna with a dielectric substrate.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.267-273
• /
• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• 한국전자파학회지:전자파기술
• /
• 제2권4호
• /
• pp.10-16
• /
• 1991

A microstrip bandpass filter using stepped impedance resonators and tapped input / output is realized with Teflon substrate, whose center frequency is 3.5 GHz and fractional bandwidth is 20%. In order to realize a wider bandwidth of 30%, the Crystal's design method and the input / output tapping scheme are used. Another microstrip filter designed as mentioned above is realized with Epsilam-10 substrate. This case shows good agreement between the theoretical responses and the measured ones.

• 한국전자파학회논문지
• /
• 제24권6호
• /
• pp.581-585
• /
• 2013

마이크로스트립 패치 안테나의 대역폭을 확장하기 위한 방안을 제시하였다. 이 안테나는 사각형의 슬롯을 가진 접지판 위에 변형된 T-자 모양의 마이크로스트립 라인으로 급전되는 구조를 갖는다. 제시된 마이크로스트 립 패치 안테나는 슬롯과 변형된 T-자 모양의 급전 라인의 크기와 위치를 최적화시킴으로써 광대역 특성을 구현 하였다. 컴퓨터 모의실험 결과에 의하면 VSWR 2:1 기준에서 127.8 %(0.65~2.95 GHz)의 대역폭을 얻을 수 있었다.

• Journal of electromagnetic engineering and science
• /
• 제8권4호
• /
• pp.144-147
• /
• 2008

This paper proposes a tunable combline bandpass filter with high selectivity, constant bandwidth, and good stopband performances. A filter with these characteristics is obtained by applying cross-coupling to the conventional combline bandpass filter using stepped-impedance resonators(SIRs). For high selectivity and constant bandwidth, cross-coupling is utilized and the SIR configuration is used for enhanced stopband performances. The proposed combline tunable bandpass filter with 5% of fractional bandwidth at 1.6 GHz was fabricated and tested. The measured results showed 11.6% tunability with constant bandwidth, high selectivity and enhanced stopband characteristics.

• 한국전자파학회논문지
• /
• 제29권5호
• /
• pp.397-400
• /
• 2018

본 논문에서는 칩 면적을 최소화한 65 nm CMOS 기반 30~46 GHz 대역 광대역 증폭기 회로의 설계 및 측정결과에 대하여 기술하였다. 전체 증폭기의 칩 면적을 줄이기 위해 결합 인덕터를 이용한 임피던스 정합회로를 사용하였다. 제작된 광대역 증폭기 회로는 9.3 dB 최대 이득, 16 GHz의 3 dB 대역폭 및 42 % 비대역폭 등의 측정 결과를 보였다. 입출력 반사 손실은 각각 35.8~46.0 GHz 대역과 28.6~37.8 GHz 대역에서 10 dB 이상이다. 공급 전압은 1.2 V이며, 소비 전력은 42 mW이다. 3 dB 대역폭 내에서의 군 지연 변화는 19.1 ps이며, 패드를 제외한 칩 면적은 $0.09mm^2$이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권3호
• /
• pp.179-192
• /
• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• 한국전자파학회논문지
• /
• 제18권2호
• /
• pp.126-135
• /
• 2007

본 논문은 기존에 제시된 집중 소자 캐패시터와 접지를 이용한 평행 결합 선로 필터의 소형화 기법이 갖는 대역폭 감소 문제를 해결하는 기법을 제안하였다. 평행 결합 선로 필터는 그 설계 및 제작이 쉬워 RF(Radio Frequency) 필터로 많은 응용이 이루어지고 있다. 이러한 평행 결합 선로 필터에 대하여 기존에 제시된 집중 소자 캐패시터와 접지를 이용한 소형화 기법은 적은 수의 캐패시터만을 이용하여 필터를 소형화할 수 있으며, 더불어 고조파 특성의 개선 및 스컷 특성의 개선 등의 부가적인 장점이 있는 기법이나 제시된 기법을 이용하여 필터를 소형화할 경우 대역폭이 감소한다는 문제점을 가지고 있었다. 본 논문에서는 이러한 대역폭의 감소를 필터를 구성하는 각 단의 평행 결합 선로의 군지연 변화를 계산하여 대역폭의 감소의 정도를 유추하고, 역으로 대역폭이 감소하는 만큼 사전에 필터의 대역폭을 크게 설계함으로 소형화로 인한 대역폭의 감소를 해결하는 방법을 제시하였다. 제안된 기법에 대한 검증을 위해 테프론(${\varepsilon}_r=2.2$) 기판을 사용하여 무선 랜 대역인 5.2 GHz대역의 FBW(Fractional Band Width) 10%의 필터를, 제안한 기법을 적용하여 공진기의 길이를 ${\lambda}/4$로 줄인 헤어핀 형태로 제작 및 측정하여 제안된 기법의 타당성을 확인하였다.

• Journal of electromagnetic engineering and science
• /
• 제3권2호
• /
• pp.104-110
• /
• 2003

A ring filter is proposed as a wide-banded filter. It consists of a ring and two short stubs, which are connected at 90$^{\circ}$ and 270$^{\circ}$ points of the ring. Since the termination impedance at 90$^{\circ}$ and 270$^{\circ}$ points of the ring and the characteristic impedance of the short stub have an effect on designing of it, the relation between them and bandwidths has been studied. Based on the study, two types of small-sized wideband CVT(constant VSWR-type impedance transformer)- and CCT(constant conductance-type impedance transformer)-ring filters are introduced, designed, simulated and one of two, a CCT -ring filter, is tested. The circumference of the ring can be reduced theoretically up to 60$^{\circ}$ and two of many cases having about 300$^{\circ}$ circumferences are simulated. The simulated results show more than 100 % fractional bandwidth, which can be obtained with more than 5 stages in conventional filter-design techniques. To test the designed CCT-ring filter, it has been fabricated in microstrip technology and the measured results show good agreement with the simulated ones, having more than 100 % fractional bandwidth.

• Journal of information and communication convergence engineering
• /
• 제21권1호
• /
• pp.1-8
• /
• 2023

This paper presents a design method for a wideband bandpass filter (BPF) which compensates for frequency dependency based on the image admittance and image phase. In the proposed method, new compensation methods for the admittance and phase are integrated with the conventional method. The proposed method improves the frequency shift and reduces the unwanted bandwidth when designing more than 20% of the Fractional Bandwidth (FBW), whereas the conventional method exhibits frequency degradation at only 10% FBW. The proposed design theory was verified by applying it to both lumped elements and distributed lines through circuit simulation and measurements without an optimization process. The measurement results demonstrate improvements in the frequency shift and target bandwidth. In the future, an accurate design method based on frequency dependence can be implemented for the next-generation broadband communication system applications.