• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Korean Chemical Society
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• v.58 no.6
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• pp.560-568
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• 2014

The contribution of electrostatic interactions to protein folding reaction was studied by using mutant ubiquitin with lysine to alanine mutation at residue position 29. Based on the three dimensional structure of ubiquitin, lysine 29 is located close to negatively charged glutamate 16 and aspartate 21 and considered to stabilize the native state of ubiquitin by electrostatic interactions between these residues. The equilibrium unfolding experiment showed that the native stability was decreased by about ~20% upon mutation. This observation indicates lysine 29 indeed forms electrostatic interactions with nearby residues. Folding kinetics measurements using stopped-flow device and quantitative analysis of kinetics data indicate that ubiquitin folds from unfolded state to native state via intermediate state as observed previously. This intermediate state was observed to form immediately after the initiation of folding reaction. The folding intermediate was shown to be destabilized considerably upon lysine to alanine mutation. These observations indicate that electrostatic interactions can form early stage of protein folding and hence lead the folding reaction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.66-71
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• 2000

A new Soft Recovery Quasi-Resonant Converter (SR QRC) haying multiple order folding snubber network is proposed. It is combined with normal quasi-resonant converter with folding snubber network of which the surrounding components are composed of diodes and capacitors. The reverse recovery loss of main rectifier diode is eliminated by this method utilizing multiple resonance. The proposed converter has PWM capability with high efficiency and is suitable for high voltage and high power applications. By extension of this concept to other switching converters, a new family of SR PW QRC may be developed.

• Structural Engineering and Mechanics
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• v.75 no.2
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• pp.229-237
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• 2020

The steel slit shear wall (SSSW), made by cutting vertical slits in a steel plate, is increasingly used for the seismic protection of building structures. In the domain of thin plate shear walls, the out-of-plane buckling together with the potential fracture developed at slit ends at large lateral deformation may result in degraded shear strength and energy dissipation, which is not desirable in view of seismic design. To address this issue, the present study proposed a new type of SSSW made by intentionally introducing initial out-of-plane folding into the originally flat slitted plate. Quasi-static cyclic tests on three SSSWs with different amplitudes of introduced out-of-plane folding were conducted to study their shear strength, elastic stiffness, energy dissipation capacity and buckling behavior. By introducing proper amplitude of out-of-plane folding into the SSSW fracture at slit ends was eliminated, plumper hysteretic behavior was obtained and there was nearly no strength degradation. A method to estimate the shear strength and elastic stiffness of the new SSSW was also proposed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.57-64
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• 2003

Recently, it has been shown that cryptographic devices such as smart cards are vulnerable to power attacks. In this paper, by mixing the randomization concept and the folding in half for secret scalar integer on ECCs, we propose an efficient and fast scalar multiplication algorithm to resist against simple power analysis(SPA) and differential power analysis(DPA) attacks. Our proposed algorithm as a countermeasure against SPA and DPA is estimated as a 33% speedup compared to the binary scalar multiplication.

• Honam Mathematical Journal
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• v.34 no.3
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• pp.423-438
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• 2012

In this paper, we discuss numbers of downwards and upwards in generalized paper folding sequences. We compute the exact number of downwards and upwards in $R^n_p$ and $(R_pR_q)^n$ by using the properties of recursive sequences where n, p and q are natural numbers with $p{\geq}2$ and $q{\geq}2$.

• The Mathematical Education
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• v.41 no.1
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• pp.79-90
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• 2002

In this article we study on connecting paper 131ding activities of triangle with mathematical proof Folding median, bisector of angle, and hight of paper triangle, we from and extract some ideas that help us to proof some important theorems of plane geometry. In this study using formed ideas in the process of paper folding activities, we suggest some interesting new mathematical proofs of the following theorems: 1. three medians of triangle are intersect in a point; 2. three bisectors of interior angles of triangle are intersect in a point; 3. three heights of triangle are intersect in a point.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.657-660
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• 2000

This paper proposes a Data-Flow-Graph (DFG) restructuring to reduce calculating errors in loop folding scheduling. The prime cause of calculating error is rounding errors due to the restriction of the operation digit of functional units. This rounding error is increased more by using multipliers than adders, so reducing the number of multiplications and putting off them as much as possible reduce rounding errors. The proposed approach reduces the number of multiplications by restructuring DFG in loop folding.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.185-189
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• 2003

최근 스마트카드에 대한 수요가 증가함에 따라 스마트카드에 대한 보안상의 문제가 대두되고 있다. 스마트카드의 안전성을 위협하는 공격 방법 중 전력공격은 가장 강력한 공격으로 많은 연구가 되고 있다. 본 논문에서는 전력분석 공격의 한 방법인 MESD 공격에 대해 알아보고 이에 대한 대응 방법으로 제안된 RSM 알고리듬에 대해 알아본다. 또한 이 알고리듬의 연산 속도 향상을 위해 folding 기법을 사용한 알고리듬에 대해서도 알아보고 MESD 공격에 안전한지를 실험을 통해 검증한다.