• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of IKEEE
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• v.16 no.1
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• pp.45-50
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• 2012

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.18-24
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• 2007

As VLSI technology scales to nano-meter order, relatively increasing global wire-delay has added complexity to system design. Global wire-delay could be reduced by inserting pipeline-elements onto wire but it should be coupled with LIP(Latency Intensive Protocol) to have correct system timing. This combination however, drops the throughput although it ensures system functionality. In this paper, we propose a computation method useful for minimizing throughput deterioration when pipeline-elements are inserted to reduce global wire-delay. We apply this method while placing blocks in the floorplanning stage. When the necessary for this computation is reflected on the floorplanning cost function, the throughput increases by 16.97% on the average when compared with the floorplanning that uses the conventional heuristic throughput-evaluation-method.

• Korean Institute of Interior Design Journal
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• v.16 no.6
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• pp.106-115
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• 2007

The Werkbund housing exhibitions in Europe in the 20's and 30's presented various planning concepts and played a important roll for modernization of housing Architecture. This study, therefore, aims to understand the contemporary issues of housing in this period, which showed the meaningful momentum for housing plans today. In order to grasp the general characteristics of exhibition housing the representative cases -Weissenhofsiedlung, Dammerstock, Breslausiedlung, Werkbund Siedlung in $Z\"{u}rich-Neub\"{u}hl$, Werkbundsiedlung Wien und BaBa- were throught documents analyzed. The architects offered an innovative building typology such as row housing and new prototype of housing units accordingly social needs. Especially, In this study housing unitplans were in 6 groups such as flexible type, cabin type, free open plan, Raumplan, functional 2-story type and corridor type categorized. And they were analyzed how deeply technological development, architectural design perceptions as well as functional aspects had on the planning of floorplans reflected. As a result, in the housing exhibitions various architectural ideas presented the "Zeitgeist" not only such as improvement of physical environment of housing, but also such as rationalization, standardization, functionalization, normalization of housing architecture. Also their unitplans corresponded to newly developed building typology and modern household type. As well as they represented notable spatial concepts. Moreover it contributed to create a new paradigm of housing for the new epoch.

• Journal of the Korean Institute of Intelligent Systems
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• v.6 no.3
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• pp.73-80
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• 1996

In this paper, a new method of finding a sub-optimal solution of an autoplacer which places electrical components autiomatically in PCB CAD tools. The software implementation of the proposed method can be viewed as a new type of floorplan based on evolutionary programming. To solve this problem, three kinds of operators and a fitness function are designed. Computer simulation results demonstrate the usefulness and effectiveness of the proposed scheme in the light of computation time and effort.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.482-486
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• 2007

본 논문은 기존의 O-tree 표현법을 이용한 플로어플랜 알고리즘의 결점을 보완한 새로운 알고리즘을 제안한다. 기존의 방법에선 플로어플랜의 변형을 처리하는 과정에서 몇 가지 변형을 간과하기 때문에 좋은 해를 놓치는 경우가 발생한다. 본 논문에서는 기존의 방법을 수정하여 변형을 처리하는 과정에서 블록이 들어갈 수 있는 모든 위치를 고려하였다. 그 결과 MCNC 밴치마크 회로를 이용한 실험에서 총면적이 이전의 방법에 비해 평균 3% 개선되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.234-237
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• 2009

CBL[1](Corner Block List)에 기반한 Non-Slicing 플로 플랜 알고리즘은 빈 공간이 없는 Non-Slicing 플로플랜만 나타낼 수 있다. 본 논문에서는 CBL 단점을 보완하고 실제 블록의 크기를 이용하여 최적의 위치에 블록을 배치 하기 위해 contour map을 이용할 것을 제시한다. 본 알고리즘은 배치시 면적을 최소화 하는 방법을 제시하므로 CBL의 단점을 해결하고 더불어 최적해를 찾기 위한 실행 시간을 단축 시키는 효과를 기대할 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• Journal of IKEEE
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• v.16 no.3
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• pp.197-202
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• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.497-501
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• 2007

BSG(Bounded Sliceline Grid)를 이용한 플로어플랜 기법은 매우 빠르고 효과적이나 모듈 사이에 빈 공간이 존재하여 필요 이상으로 면적을 넓게 차지하는데도 불구하고 그 점을 무시한채 배치 면적을 구하는 문제점이 있다. 본 논문에서는 BSG 구조를 이용한 플로어플랜 과정 중 빈 공간이 생기는 문제점을 해결하기 위해 모듈들을 좌측 또는 아래로 옮길 수 있는데 까지 옮기는 압축 기법을 추가하여 필요한 면적이 최소가 되도록 하였다. 실험 결과는 압축 기법을 사용하는 것이 사용하지 않을 때보다 최소 면적과 평균 면적 면에서 모두 개선되는 것을 보여 준다.