• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.250-253
• /
• 2000

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

• 한국정보통신학회논문지
• /
• 제19권2호
• /
• pp.407-413
• /
• 2015

본 논문에서 제안된 십진 부동소수점 가산기(decimal floating-point adder, DFPA)는 선행 제로 예측기(leading zero anticipator, LZA)를 이용해 임계 경로 단축을 통해 지연시간을 줄임으로서 연산 처리 속도를 향상시키는 파이프라인 구조로 설계하였다. 제안된 십진 부동소수점 가산기의 성능 평가 및 검증 환경은 시뮬레이션에 Flowrian 툴을 사용하였으며, 합성에는 QuartusII 툴 상에서 Cyclone III FPGA를 대상으로 지정하였다. 제안된 방식은 동일한 입력 데이터를 이용하여 기존에 제안된 설계 방식들과 시뮬레이션을 통해 비교 검증한 결과, L.K.Wang이 제안한 방식 및 기존 제안된 방식들보다 각각 11.2%, 5.9%의 성능이 향상되었다. 또한 연산 처리 속도 향상 및 임계 경로 상의 지연 소자의 수가 감소됨을 확인하였다.

• 한국CDE학회논문집
• /
• 제7권2호
• /
• pp.75-80
• /
• 2002

This paper details a robust and efficient algorithm for point classification with respect to a polygon in 2D real number domain. The concept of tolerance makes this algorithm robust and consistent. It enables to define‘on-boundary’ , which can be interpreted as either‘in-’or‘out-’side region, and to manage rounding errors in floating point computation. Also the tolerance is used as a measure of reliability of point classifications. The proposed algorithm is based on a ray-intersection technique known as the most efficient, in which intersections between a ray originating from a given test point and the boundary of a region are counted. An odd number of intersections indicates that the point is inside region. For practical examples the algorithm is most efficient because most edges of the polygon region are processed by simple bit operations.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.365-368
• /
• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.1089-1092
• /
• 1998

Conventional floating-point adders have one data-path that is used for all operations. This paper describes a floatingpoint adder eeveloped for low power consumption, which has three data-paths one of which is selected according to the exponent difference. The first is applied to the case that the absolute exponent difference (AED) of two operands is less than 1, and the second is for 1

• 전자공학회논문지C
• /
• 제34C권8호
• /
• pp.71-78
• /
• 1997

An LPC cepstrum processor for speech recognition is implemented on CMOS array process. The designed processor contains a 24-bit floating-point MAC unit to perform the correlation quickly, which occupies the majority of operations used in the algorithm, and has 22 register files to store temporary variables. For the purpose of fast operations, the floating-point MAC consists of a 3-stage pipeline and the new post-normalization shceme is proposed and applied to it. Experimental result shows that it takes approximately 266.mu.s to process 200 samples/frame at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of gates are 27,760.

• 대한전자공학회논문지SD
• /
• 제46권3호
• /
• pp.20-25
• /
• 2009

본 논문에서는 모바일 환경 기반의 3차원 그래픽 연산을 위한 조명처리 엔진 및 쉐이더 프로세서에 사용 가능한 제곱근과 역제곱근 연산기의 구조를 제안한다. 제안하는 구조는 Taylor 전개식을 기반으로 하여 참조 테이블 및 보정 유닛으로 구성되어 있어 참조 테이블의 크기를 줄였다. 연산 결과는 IEEE-754 표준의 단정도 32 bit 부동소수점 형식과 모바일 환경을 위하여 이를 축소한 24 bit 부동소수점 형식에 대해 OpenGL 1.x ES 에서 요구하는 $10^{-5}$의 정확도를 거의 만족한다. 제안된 구조에 따라 설계된 제곱근 및 역제곱근 연산기는 Verilog-HDL을 사용하여 설계되었으며 파라미터 변경을 통하여 24 bit와 32 bit 연산이 가능하도록 합성이 가능하고 1사이클의 잠복기를 갖는다. 설계된 연산기들의 동작은 FPGA를 이용한 검증시스템을 통하여 검증하였다.

• 전자공학회논문지A
• /
• 제28A권11호
• /
• pp.915-922
• /
• 1991

This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.

• Smart Structures and Systems
• /
• 제14권6호
• /
• pp.1131-1150
• /
• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• 한국정보통신학회논문지
• /
• 제5권3호
• /
• pp.517-524
• /
• 2001

IEEE-754 부동소수점 표준을 지원하는 radix-2 SRT 제산기 유닛을 redundant binary (RB) 수치계를 이용하여 설계하였다. RB 수치계를 이용함으로써 기존의 2의 보수 수치계를 이용하는 경우에 비해 부분 몫 결정 회로의 동작속도를 약 20-% 향상시킴과 아울러 회로 단순화를 이루었다. 또한, 새로운 RB 가산기 회로를 제안함으로써 가수 제산기를 효율적으로 구현하여 기존의 방식에 비해 면적을 약 20-%의 감소시켰다. 설계된 부동소수점 제산기는 배정도 형식과 5가지의 예외처리 및 4가지의 반올림 모드를 지원하며, Verilog HDL로 설계되어 Verilog-XL로 검증하였다.