• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.39-43
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• 2009

In this paper, the flow characteristics of underfill material driven by capillary action between flip-chip and substrate were investigated. Also, the effects of viscosity level and dispensing point of underfill on flow characteristics were investigated. Flip chip package size was $5mm{\times}5mm{\times}0.65^tmm$, the diameter of solder bump was 100 ${\mu}m$, and the pitch was 150 ${\mu}m$. It was full grid area-array type with 1024 I/Os. The glass substrate was used and the gap between the chip and substrate was 50 ${\mu}m$. For the experimental study, three different underfills with different viscous properties($2000{\sim}3700$ cps), and two different types of dispensing methods(center dot and edge dot) were used. The flow characteristics and filling time of underfill were investigated by using CCD camera. The results show that the edge flow was faster than center flow due to the edge effect, which was caused by the resistance of solder bumps. In case of edge dot dispensing type, the filling time was faster due to the large edge effect, compared to center dot dispensing type. Also, it was found that the underfill flow was faster and the filling time decreased as the viscosity level of underfill was decreased.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.661-662
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• 2006

This research is on a laser soldering using the micro solder-balls used in flip chip packaging process. A laser source used in laser soldering is Nd:YAG laser(250W and 60W). Solder-balls of 100, 300, $500{\mu}m$ size are used in experiments. The laser head to deliver a laser beam and the nozzle to transfer solder-balls are manufactured to bump solder-balls. After soldering solder-balls the shear test is carried out to determine the wetting at the interface between the surface and a solder-balls With the results of solder bumping tests a laminated molding is accomplished for manufacturing the three dimensional molding.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.27-32
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• 2002

In this paper, global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. It was estimated by the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life of results was obtained at the thermal cycling testing condition of -65℃ ∼ 150℃. It was increased about 3.5 times in comparison with that of 0℃ ∼ 100℃. As the change of pad structure at the same other conditions, the fatigue life of SMD structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.49-53
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• 2002

The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.87-119
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• 2001

Fine Pitch Technology will be accelerated among next decade. Buildup Technology is Key Technology for High Density Interconnection. Novel Base Material is critical for High Speed, Area Array Flip Chip Application. Japanese PWB Technology Roadmap will be Published soon.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.17-25
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• 2006

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $moir\'{e}$ interferometry. $Moir\'{e}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for both single and double-sided package assemblies are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one because of its symmetric structure. The largest effective strain occurred at the solder ball located on the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one by 50%.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.