• Journal of the Korean Institute of Telematics and Electronics
• /
• v.13 no.3
• /
• pp.1-6
• /
• 1976

In this paper, a method of test pattern generation for the functional failure in both combinational and sequentlal logic networks by using exterded Boole an difference is proposed. The proposed technique provides a systematic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function that represents the Logic network for which the test patterns are to be generated. The computer experimental results show that the proposed method is suitable for both combinational and asynchronous sequential logic networks. Suitable models of clocked flip flops may make it possible for one to extend this method to synchronous sequential logic networks.

• Journal of IKEEE
• /
• v.9 no.2 s.17
• /
• pp.152-160
• /
• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.6
• /
• pp.33-41
• /
• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.392-395
• /
• 1999

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

• 한국정보통신설비학회:학술대회논문집
• /
• 2006.08a
• /
• pp.179-182
• /
• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.3C no.6
• /
• pp.220-223
• /
• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.32 no.11
• /
• pp.404-416
• /
• 1983

This paper is concerned with the design automation of the sequential machines. The operations of sequential machine can be diveded into two types such as synchronous and asynchronous sequential machine and their realization is treated in separate mode. But, in order to integrate logic circuits in high volume, mixed mode sequential machine uses common circuitry that consists of gates and flip-flops. Proposed sequential machine can be designed by several method, which are hard-wired implementation, firmware realization by PLA and ROM. And then onr example shows the differnces among three design mothods. Finally, computer algorithm(called MINIPLA) is discussed for various application of mixed-mode sequential machine.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2003.09a
• /
• pp.668-671
• /
• 2003

A concept of deadlock point of fuzzy sequential circuit is proposed. There are six cases of fuzzy sequential circuits of 1 state and 1 input variables with deadlock points. Examples of each case are shown both in a form of characteristic equation and in a graphical illustration. As fuzzy sequential circuit with 1 state and 1 input variables, D and T fuzzy flip-Hops are also characterized using the proposed concept. Thus one of the four types of D fuzzy Hip-Hops and T fuzzy Hip-flop have a deadlock point 1/2.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.15 no.4
• /
• pp.1232-1245
• /
• 2021

In this study, prediction of product sales as they relate to changes in temperature is proposed. This model uses long short-term memory (LSTM), which has shown excellent performance for time series predictions. For verification of the proposed sales prediction model, the sales of short pants, flip-flop sandals, and winter outerwear are predicted based on changes in temperature and time series sales data for clothing products collected from 2015 to 2019 (a total of 1,865 days). The sales predictions using the proposed model show increases in the sale of shorts and flip-flops as the temperature rises (a pattern similar to actual sales), while the sale of winter outerwear increases as the temperature decreases.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.11-22
• /
• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.