• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.69-76
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• 2007

A new circuit design for Bus-Invert Coding is presented in this paper. The new scheme sends the coding information through the bus-lines instead of the invert-line which has been used conventionally for many types of Bus-Invert algorithms. By employing a newly developed bus-driver called Flip-Driver and a selection circuit, it not only removes the invert-line but suppresses the additional bus-transitions in sending coding information. It is verified by simulations that the efficiency of various Bus-Invert algorithms is increased about 40% to 100% by employing the new design.

• 전기의세계
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• v.13 no.3
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• pp.21-27
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• 1964

A method of triggering a series connected complementary transister flip-flop is described. Also measurements have been made for the operation region with respect to the input pulse variation. This circuit is compared with a Eccles-Jordan flip-flop when it used as a Nixie tube driver of a neon lamp driyer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.408-416
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• 2010

A dumbbell-type CPW transmission-line structure has been proposed to improve the return loss of the transmission line between a driver IC and flip-chip-bonding VCSEL(Vertical Cavity Surface Emitting Laser) in a hybrid opto-electric circuit board(OECB). The proposed structure used a pair of dummy ground solder balls on the ground lines for flip-chip bonding of the VCSEL and designed the dumbbell-type CPW transmission line to improve reflection characteristics. The simulated results revealed that the return loss of the dumbbell-type CPW transmission line was 13-dB lower than the conventional CPW transmission line. A 4-dB improvement in the return loss was obtained using the dummy ground solder balls on the ground lines. The variation rate of the reflection characteristic with the variation of terminal impedances of the transmission line (at the output terminal of the driver IC and the input terminal of the VCSEL) is about ${\pm}2.5\;dB$.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.222-223
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• 2010

TOP245P driver IC modeling technique are proposed for the LED Driver design. Analog behavioral model of TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The averaged-model and switching-model is applied to the LED driver simulation. The simulation results by the proposed TOP245P IC modeling technique are in good agreement with that in the data sheet and an experiment data.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.74-77
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• 2011

PSPICE modeling of a commercial LED driver IC (TOP245P) and PC817A optocoupler is proposed for the switch-mode power supply (SMPS) (applicable to LED driver) design and simulation. An analog behavioral model of the TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The empirical equation of PC817A current transfer ratio (CTR) is fitted from the datasheet of PC817A. Two types of SMPSs are simulated with the averaged-model and switching-model. The simulation results by the proposed PSPICE models are in good agreement with those in the data sheet and an experimental data.

• ETRI Journal
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• v.26 no.1
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• pp.1-6
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• 2004

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and ${\sqrt{T}}$-dependent thermal red shifts. We observed uniform bottom emissions from a 1-kb smart pixel chip of a $32{\times}32$ InGaAs PQR laser array flip-chip bonded to a 0.35 ${\mu}m$ CMOS-based PQR laser driver. The PQR-CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.719-726
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• 2008

In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.24-33
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• 2009

The transition of auxiliary lines for transmitting coding information has been one of the major obstacles to restricting the scalability of Sequence Switch Coding (SSC) algorithms. A new design of SSC which does not use auxiliary lines is presented in this paper. The new design makes overhead transitions far less than the previous designs that use auxiliary lines. By applying the new technique, more than 50% of overhead transitions have been reduced, leading to the increase of 30% of the overall efficiency of SSC algorithm.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.