• 마이크로전자및패키징학회지
• /
• 제9권1호
• /
• pp.35-41
• /
• 2002

솔더 범프를 이용한 플립 칩 접속 기술은 시스템의 고속화, 고집적화, 소형화 요구 덴 마이크로 일렉트로닉스의 성능은 향상시키기 위해 필요한 기술이다. 본연구 에서는 Cr/Cr-Cu/cu UBM 구조에서 고 용융점 솔더 범프와 저 용융점 솔더 범프를-시효처리 후 전단 강도를 평가하였다. 계면에서 관찰된 금속간 화합물의 성장과 접합상태를 SEM과 TEM으로 분석하였으며, 유한요소법을 통하여 전단하중을 적용하였을때 집중되는 응력을 해석하였다. 실험결과 Sn-97wt%Pb와 Sn-37wt%Pb에서 900시간 시효 처리된 시편의 전단강도는 최대 값에서 각각 25%, 20% 감소하였다. 시효처리를 통해 금속간화합물인 $Cu_6/Sn_5$와 $Cu_3Sn$의 성장을 확인하였으며, 파단 경로는 초기의 솔더 내부에서 IMC층의 계면으로 이동하는 경향을 알 수 있었다.

• 마이크로전자및패키징학회지
• /
• 제30권3호
• /
• pp.1-10
• /
• 2023

최근, 고사양 컴퓨터, 모바일 제품의 수요가 증가하면서 반도체 패키지의 고집적화, 고밀도화가 요구된다. 따라서 많은 양의 데이터를 한 번에 전송하기 위해 범프 크기 및 피치 (Pitch)를 줄이고 I/O 밀도를 증가시킬 수 있는 플립 칩 (flip-chip), 구리 필러 (Cu pillar)와 같은 마이크로 범프 (Micro-bump)가 사용된다. 하지만 범프의 직경이 70 ㎛ 이하일 경우 솔더 (Solder) 내 금속간화합물 (Intermetallic compound, IMC)이 차지하는 부피 분율의 급격한 증가로 인해 취성이 증가하고, 전기적 특성이 감소하여 접합부 신뢰성을 악화시킨다. 따라서 이러한 점을 개선하기 위해 UBM (Under Bump Metallization) 또는 Cu pillar와 솔더 캡 사이에 diffusion barrier 역할을 하는 층을 삽입시키기도 한다. 본 review 논문에서는 추가적인 층 삽입을 통해 마이크로 범프의 과도한 IMC의 성장을 억제하여 접합부 특성을 향상시키기 위한 다양한 연구를 비교 분석하였다.

• Journal of Welding and Joining
• /
• 제21권2호
• /
• pp.97-101
• /
• 2003

The change of microstructures in the base metal during transient liquid phase bonding process of directionally Ni base superalloy, GID-111 was investigated. Bonds were fabricated using a series of holding times(0~7.2ks) at three different temperatures. The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of samples was evaluated. A TiW/Cu/electroplated Cu UBM structure was selected and the samples were aging treated to analyze the effect of intermetallic compounds with the time variations. An FIB technique was applied to the preparation of samples for TEM observations. An FIB technique is very useful to prepare TEM thin foil specimens from the solder joint interface. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the solder and the UBM was observed by using SEM, TEM and EDS. As a result, the shear strength was decreased of about 21% in the 100${\mu}{\textrm}{m}$ sample at 17$0^{\circ}C$ aging compared with the maximum shear strength of the sample with the same pad size. In the case of the 12$0^{\circ}C$ aging treatment, 18% of decrease in shear strength was measured at the 100${\mu}{\textrm}{m}$ pad size sample. An intermetallic compound of Cu6Sn5 and Cu3Sn were also observed through the TEM measurement by using.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
• /
• pp.74-79
• /
• 2000

In an attempt to estimate the wetting properties of wettable metal layers by wetting balance method, an analysis of wetting curves of the coating layer was performed. Based on the analysis, wetting properties of UBM-coated Si-plate were estimated by the new wettability indices. The wetting curves of the one and both sides-coated UBM layers have the similar shape and show the similar tendency to the temperature. So the wetting property estimation of one side coating is possible with wetting balance method. For UBM of Si-chip, Cr/Cu/Au UBM is better than Ti/Ni/Au in the point of wetting time. At general reflow temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) is better than that of few melting point ones(Sn-Bi, Sn-In).The contact angle of the one side coated plate to the solder can be calculated from the farce balance equation by measuring the static state force and the tilt angle.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2008년도 추계학술대회B
• /
• pp.2750-2753
• /
• 2008

This paper introduce the CFD analysis for predicting the heat transfer at the Ultrasonic horn. Approximately Ultrasonic horn separates two part. One is preheating part and the other is cooling part. Temperature of preheating part rise up by $260^{\circ}C$ that make it possible to attach a chip to a semiconductor. Also there is a piezo material in the cooling part. When piezo work, it generates heat of $100^{\circ}C$. It can stand by $150^{\circ}C$. But the high temperature conducted from the preheating part has a bad affect on the piezo. These situation make it necessary cooling at piezo. Previously except of the piezo, all of them are composed of the SUS440c that has good thermal conductivity. This study shows way that not only cooling the piezo but also cutting off the conduction between preheating part and cooling part by using the Ti and Duralumin that have low thermal conductivity compare with the SUS440c. Conclusion of CFD analysis that the heat coming from the piezo can't be transferred the horn cause of the Ti and Duralumin.

• 전자통신동향분석
• /
• 제28권5호
• /
• pp.100-110
• /
• 2013

플립 칩 본딩 기술은 1960년대에 개발된 기술이지만 가격 경쟁력, 경박단소(輕薄短小)의 부품 구현, 뛰어난 전기적 특성으로 인해 최근에 와서 다시금 주목 받고 있고, 관련 시장이 지속적으로 성장하고 있는 분야이다. 기술 응용 분야로는 스마트 폰, 타블렛 PC 등 개인 휴대 단말기에서 고성능 서버, 게임 컨트롤로 등 다양한 제품을 아우르고 있다. 미세 피치의 경우 관련 시장이 2018년까지 연평균 35%의 폭발적인 성장을 보일 것으로 예측되고 있다. 따라서, 국내외 기업, 연구소, 학계 등에서 활발한 연구 활동이 진행되고 있다. 본고에서는 플립 칩 본딩 기술의 세부 기술을 살펴보며 동시에 피치에 따라 각 세부 기술에 있어 최근에 개발되고 있는 기술 동향을 논의하고자 한다.

• 마이크로전자및패키징학회지
• /
• 제18권1호
• /
• pp.7-13
• /
• 2011

According to increasing of data transfer rate, printed circuit board (PCB) is required improvement of transmission speed. Optical PCB and its packaging technology can be one of the solutions that overcome the limitations of conventional electrical PCB. The data transmission capacity will be increased 10 Tbps at 2015. To this end, studies on various OPCB technologies are being conducted. For cost-effective and high- performance OPCB, studies of optical coupling by polymer replication process are conducted. In this work, optical waveguide and optical fiber array block were sequentially fabricated by polymer pattern replication method. Using this method we successfully demonstrate low loss optical fiber coupling between optical waveguide and optical fiber arrays. And researches on flip chip bonding process and using electro-optic connectors for packaging are conducted.

• ETRI Journal
• /
• 제35권2호
• /
• pp.340-343
• /
• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• ETRI Journal
• /
• 제33권4호
• /
• pp.637-640
• /
• 2011

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip-chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 ${\mu}m$ in one direction.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2015년도 춘계학술대회 논문집
• /
• pp.31-31
• /
• 2015

본 연구는, TAB(Tape Automated Bonding)접속이나 Flip Chip 접속에 의한 패캐징을 실현시키기 위해, 실리콘 웨이퍼 표면에 구리 필러 및 주석 합금을 전기 도금법으로 형성하는 전기 접점용 범프에 관한 것이다. 본 연구에서는, 균일 범프 두께, 범프 표면의 균일화, 범프 내의 보이드 발생 문제 해결, 균일한 합금 조성 및 도금 속도의 고속화를 위해, Cu 도금액 및 Sn-Ag 도금액의 첨가제에 의한 표면 형상의 제어를 중심으로 그 성능에 대해 보고한다.