• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.155-161
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• 2018

A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.4
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• pp.40-46
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• 1998

Leakage phenomena of flip-chip structures on common GaAs and alumina main substrates are characterized using the spectral domain approach to reduce the possible chip-to-chip crosstald and transmission resonance. We have found taht the longitudinal section magnetic mode is dominant for the coplanar waveguide leakage andthe leakage can be suppreassed by properly managing the gap height and the main substrate thickness in addition to the dielectric constant. These calculation results will be helpful for designing and flip-chip packagaing of high-frequency integrated circuits.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Journal of Welding and Joining
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• v.26 no.3
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.39-44
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• 2015

We investigated the effect of CNT-Ag composite pad on the contact resistance of flip-chip joints, which were formed by flip-chip bonding of Cu/Au chip bumps to Cu substrate metallization using anisotropic conductive adhesive. Lower contact resistances were obtained for the flip-chip joints which contained the CNT-Ag composite pad than the joints without the CNT-Ag composite pad. While the flip-chip joints with the CNT-Ag composite pad exhibited average contact resistances of $164m{\Omega}$, $141m{\Omega}$, and $132m{\Omega}$ at bonding pressures of 25 MPa, 50 MPa, and 100 MPa, the flip-chip joints without the CNT-Ag composite pad had an average contact resistance of $200m{\Omega}$, $150m{\Omega}$, and $140m{\Omega}$ at each bonding pressure.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.49-52
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• 2022

As the difficulty of flip chip products increase, interest in stable PKG material technology from the viewpoint of reliability is increasing. Currently, the representative of poor reliability that are mainly occurring in flip chip PKG are Sn bridge and Cu dendrite. Two type defects are caused by void generated by the flux residue around the bump. In order to essentially minimize the risk of this type of reliability failure, the linkage between the composition of Molded Under-fill (MUF) and flux, which is related material, was reviewed. In this study, the correlation between base resin and filler, which is the main component of MUF, and flux, was defined, and the material composition design was carried out by refer to lesson learn. With the current material composition, it was confirmed that moisture absorption reliability 85%/85%/24hrs pass result and void did not occur during destructive analysis, and developed MUF has shown flux immunity improving result in flip Chip PKG. We think this study can be used in yield enhancement of flip chip process and give insights to study in compatibility between MUF and flux.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1717-1722
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• 2003

In this paper we developed flip-chip bonder using XY stage, liner-rotary actuator and vision system. We depicted the major parts of the developed flip-chip bonder. Then we discussed several problems and their solutions such as vision and motion control, pick-up module position accuracy, separation of chip from the blue taped hoop, etc. We used a post guide to improve the horizontal positional accuracy against the long arm. Also, we used an ejector module and synchronization technique for easy chip separation from the blue tape.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.1
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• pp.120-125
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• 2008

A flip-chip bonding system using DPSS(Diode Pumped Solid State) Nd:YAG laser(wavelength : 1064nm) which shows a good quality in fine pitch bonding is developed. This laser bonder can transfer beam energy to the solder directly and melt it without any physical contact by scanning a bare chip. By using a laser source to heat up the solder balls directly, it can reduce heat loss and any defects such as bridge with adjacent solder, overheating problems, and chip breakage. Comparing to conventional flip-chip bonders, the bonding time can be shortened drastically. This laser precision micro bonder can be applied to flip-chip bonding with many advantage in comparison with conventional ones.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.