• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.158-158
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• 2008

모바일 정보통신기기를 중심으로 실장모듈의 초소형화, 고집적화로 인해 접속단자의 피치가 점점 미세화 됨에 따라 플립칩 본딩용 접착제에 함유되는 무기충전제인 실리카 필러의 크기도 미세화되고 있다. 본 연구에서는 NCP (non-conductive paste)의 실리카 필러의 크기가 COB(chip-on-board) 플립칩 패키지의 신뢰성에 미치는 영향을 조사하였다. 실험에 사용된 실리카 필러는 Fused silica 3 종과 Fumed silica 3종이며 response surface 실험계획법에 따라 혼합하여 최적의 혼합비를 정하였다. 테스트베드로 사용된 실리콘 다이는 투께 $700{\mu}m$, 면적 5.2$\times$7.2mm로 $50\times50{\mu}m$ 크기의 Au 도금범프를 $100{\mu}m$ 피치, peripheral 방식으로 형성시켰으며, 기판은 패드를 Sn으로 finish 하였다. 기판을 플라즈마 전처리 후 Panasonic FCB-3 플립칩 본더를 이용하여 플립칩 본딩을 수행하였다. 패키지의 신뢰성 평가를 위해 $-40^{\circ}C{\sim}80^{\circ}C$의 열충격시험과 $85^{\circ}C$/85%R.H.의 고온고습시험을 수행하였으며 Die shear를 통한 접합 강도와 4-point probe를 통한 접속저항을 측정하였다.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.21-28
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• 2010

Creep behaviors of the solder balls in a flip chip package assembly during thermal cycling test is investigated.. A material models used in the finite element analysis are viscoplastic model introduced by Anand and creep model called partitioned model. Experiment of two temperature cycles using moir$\acute{e}$ interferometry is conducted to verify the reliability of material models for the analysis of thermo-mechanical behavior. Bending deformations of the assemblies and average strains of the solder balls due to temperature change and dwell time are investigated. The results show that time-dependent shear strain of solder by the partitioned model is in excellent agreement with those by moir$\acute{e}$ interferometry, while there is considerable difference between results by Anand model and experiment. In this paper, the partitioned model is employed for the time-dependent creep analysis of the FC-PBGA package. It is also shown that the thermo-mechanical stress becomes relaxed by creep behavior at high temperature during temperature cycles.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.55-62
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• 2019

Stiffness-gradient stretchable electronic packages of the soft PDMS/hard PDMS/FPCB structure were processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff flexible printed circuit board (FPCB) as the island substrate. The elastic characteristics of the stretchable packages were estimated and their long-term reliabilities on stretching cycles and bending cycles were characterized. With 0.28 MPa, 1.74 MPa, and 1.85 GPa as the elastic moduli of the soft PDMS, hard PDMS, and FPCB, respectively, the effective elastic modulus of the soft PDMS/hard PDMS/FPCB package was estimated as 0.6 MPa. The resistance of the stretchable packages varied for 2.8~4.3% with stretching cycles ranging at 0~0.3 strain up to 15,000 cycles and for 0.9~1.5% with 15,000 bending cycles at a bending radius of 25 mm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.242-242
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• 2006

Increasingly complex tasks are performed by computers or cellular phone, requiring more and more memory capacity as well as faster and faster processing speeds. This leads to a constant need to develop more highly integrated circuit systems. Therefore, there have been numerous studies by many engineers investigating circuit patterning. In particular, PCB including module/package substrates such as FCB (Flip Chip Board) has been developed toward being low profile, low power and multi-functionalized due to the demands on miniaturization, increasing functional density of the boards and higher performances of the electric devices. Imprint lithography have received significant attention due to an alternative technology for photolithography on such devices. The imprint technique. is one of promising candidates, especially due to the fact that the expected resolution limits are far beyond the requirements of the PCB industry in the near future. For applying imprint lithography to FCB, it is very important to control thermal properties and mechanical properties of dielectric materials. These properties are very dependent on epoxy resin, curing agent, accelerator, filler and curing degree(%) of dielectric materials. In this work, the epoxy composites filled with silica fillers and cured with various accelerators having various curing degree(%) were prepared. The characterization of the thermal and mechanical properties wasperformed by thermal mechanical analysis (TMA), thermogravimetric analysis (TGA), differential scanning calorimetry (DSC), rheometer, an universal test machine (UTM).