• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.9-17
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• 2003

In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature ($T_g$) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and $T_g$. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

• 마이크로전자및패키징학회지
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• 제29권2호
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• pp.49-52
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• 2022

Flip Chip 제품 난이도 증가에 따라 신뢰성 관점에서 안정적인 Package (이하 PKG) 소재 기술에 대한 관심이 점차 높아지는 추세이다. 현재 flip chip PKG의 주요 신뢰성 불량은 Sn bridge와 Cu 확산 이다. 위 2가지 형태 모두 본질적으로는 bump 주변 잔류한 flux residue에 의하여 발생한 미세 공극이 유발하는 불량이다. 이러한 형태의 신뢰성 불량 발생 문제점을 최소화하기 위해 Molded Under-Fill (이하 MUF) 소재의 핵심 조성과 flux 간 상관 관계를 검토하였다. 금번 연구를 통하여 MUF 소재의 main 구성 요소인 base resin, filler와 flux에 대한 상관 관계를 정의 하였으며, 이러한 lesson learn을 토대로 flux immunity가 개선된 MUF 소재 조성을 설계할 수 있었다. 현재 해당 소재 조성으로 흡습 신뢰성 85%/85%/24hrs 확보와 파괴 분석으로 bump 주변 미세 공극의 미 발생을 확인 하였다. 본 연구 결과는 양산 단계에서의 flip chip 공정 수율 향상과 MUF와 flux 간 상용성 연구에 대한 이해를 돕는데 기여할 것으로 예상된다.

• 대한기계학회논문집A
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• 제41권6호
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• pp.443-453
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• 2017

반도체 플립칩 패키지에서 구리기둥 범프 기술은 미세 피치 및 높은 I/O 밀도로 인해 기존의 솔더 범프 접합 기술을 대체하는 중이다. 그러나 구리기둥 범프는 리플로우 접합 공정 사용 시, 구리 범프의 높은 강성으로 인해 패키지에 높은 응력을 초래한다. 따라서 최근에 플립칩 공정에서 발생하는 패키지의 높은 응력 및 휨을 감소시키기 위해 열압착 공정 기술이 시도되고 있다. 본 연구에서는 플립칩 패키지의 열압착 공정과 리플로우 공정에서 발생하는 휨에 대해 수치해석을 이용하여 분석하였다. 패키지의 휨 최소화를 위한 본딩 공정 조건 최적화를 위해 본딩 툴 및 스테이지의 온도, 본딩 압력에 대한 휨 영향을 검토하였다. 또한 칩과 기판의 면적 및 두께가 패키지의 휨에 주는 영향을 분석하였다. 이를 통해, 향후 미세피치 접합부 형성 시 휨 및 응력을 최소화하기 위한 가이드라인을 제시하고자 하였다.

• 마이크로전자및패키징학회지
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• 제15권3호
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• pp.9-17
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• 2008

전기도금법으로 Cu 머쉬룸 범프를 형성하고 Sn 기판 패드에 플립칩 본딩하여 Cu 머쉬룸 범프 접속부를 형성하였으며, 이의 접속저항을 Sn planar 범프 접속부와 비교하였다. $19.1\sim95.2$ MPa 범위의 본딩응력으로 형성한 Cu머쉬룸 범프 접속부는 $15m\Omega$/bump의 평균 접속저항을 나타내었다. Cu머쉬룸 범프 접속부는 Sn planar범프 접속부에 비해 더 우수한 접속저항 특성을 나타내었다. 캡 표면에 $1{\sim}w4{\mu}m$ 두께의 Sn 코팅층을 전기도금한 Cu 머쉬룸 범프 접속부의 접속저항은 Sn 코팅층의 두께에 무관하였으나 캡 표면의 Sn코팅층을 리플로우 처리한 Cu머쉬룸 범프 접속부에서는 접속저항이 Sn 코팅층의 두께와 리플로우 시간에 크게 의존하였다.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.245-247
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• 2007

Sn-base solder bump is mainly used in micro-joining for flip chip package. The quantity of intermetallic compounds that was formed between Cu pad and solder interface importantly affects reliability. In this research, micro-bump was fabricated by two binary electroplating and the intermetallic compounds(IMCs) was estimated quantitatively. When the micro Sn-Ag solder bump was made by electroplating, SiC powder was added in the plating solution for protecting of intermetallic growth. Then, the intermetallic compounds growth was decrease with increase of amount of SiC power. However, if the mount of SiC particle exceeds 4 g/L, the effect of the growth restraint decrease rapidly.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.49-53
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• 2002

The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

• 한국전자파학회논문지
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• 제24권12호
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• pp.1120-1127
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• 2013

본 논문에서는 칩온웨이퍼(Chip on Wafer: CoW) 공정기술을 이용한 새로운 칩온칩(Chip on Chip: CoC) 플립칩 범프 구조들을 제안하여 설계, 제작하고, 초고주파 영역에서의 응답 특성을 분석하였다. Cu 필러(Pillar)/SnAg, Cu 필러/Ni/SnAg의 기존 범프들, 그리고 SnAg, Cu 필러/SnAg, Cu 필러/Ni/SnAg를 Polybenzoxazole(PBO)로 보호한 새로운 범프들을 구성하여 웨이퍼의 $2^{nd}$ Polyimide(PI2) 층의 도포 유무에 따라 10가지 형태의 CoC 샘플들을 구조 설계하였고, 20 GHz까지의 주파수 특성이 고찰되었다. 측정 결과를 고려할 때 PI2 층이 도포된 소자들이 본 실험에 사용된 배치 플립칩 공정에 더 적합함을 알 수 있었고, 18 GHz에서 평균 0.14 dB의 삽입 손실을 보였다. 미세 패드 간격을 가지는 칩의 패키지 용도로 새로 개발된 범프들의 삽입 손실(0.11~0.14 dB)은 기존 범프들의 삽입 손실(0.13~0.17 dB)과 비교해 18 GHz까지 유사한 성능을 보이거나, 다소 좋은 특성을 보여 높은 집적도를 요구하는 다양한 초고주파 패키지에 활용될 수 있음이 확인되었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.195-202
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• 2003

In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• 한국공작기계학회논문집
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• 제16권6호
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• pp.181-186
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• 2007

UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes