• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.286-291
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• 2013

In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.61-71
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• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

• Korean Journal of Metals and Materials
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• v.46 no.9
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• pp.585-592
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• 2008

Flip-chip bonding using Cu-Sn mushroom bumps composed of Cu pillar and Sn cap was accomplished, and the contact resistance and the thermal cycling reliability of the Cu-Sn mushroom bump joints were compared with those of the Sn planar bump joints. With flip-chip process at a same bonding stress, both the Cu-Sn mushroom bump joints and the Sn planar bump joints exhibited an almost identical average contact resistance. With increasing a bonding stress from 32 MPa to 44MPa, the average contact resistances of the Cu-Sn mushroom bump joints and the Sn planar bump joints became reduced from $30m{\Omega}/bump$ to $25m{\Omega}/bump$ due to heavier plastic deformation of the bumps. The Cu-Sn mushroom bump joints exhibited a superior thermal cycling reliability to that of the Sn planar bump joints at a bonding stress of 32 MPa. While the contact resistance characteristics of the Cu-Sn mushroom bump joints were not deteriorated even after 1000 thermal cycles ranging between $-40^{\circ}C$ and $80^{\circ}C$, the contact resistance of the Sn planar bump joints substantially increased with thermal cycling.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.19 no.2
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• pp.157-162
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• 2010

This paper describes the thermal fatigue life prediction models for 95.5Sn-4.0Ag-0.5Cu solder joints of Flip chip package considering Under Bump Metallurgy(UBM). A 3D Finite element slice model was used to simulate the viscoplastic behavior of the solder. For two types of solder bump pitches, simulations were analyzed and the effects of underfill packages were studied. Consequently, it was found out that solder joints with underfill had much better fatigue life than solder joints without underfill, and solder joints with $300{\mu}m$ bump pitch had a longer thermal fatigue life than solder joints with $150{\mu}m$ bump pitch. Through the simulations, flip chip with lead-free solder joints should be designed with underfill and a longer bump pitch.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.253-257
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• 2003

The low temperature flip chip technique is applied to the package of the temperature-sensitive devices for LCD systems and image sensors since the high temperature process degrades the polymer materials in their devices. We will introduce the various low temperature flip chip bonding techniques; a conventional flip chip technique using eutectic Bi-Sn (mp: $138^{\circ}C$) or eutectic In-Ag (mp: $141^{\circ}C$) solders, a direct bump-to-bump bonding technique using solder bumps, and a low temperature bonding technique using low temperature solder pads.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.874-878
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• 2001

Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.82-82
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• 1995

• Proceedings of the KWS Conference
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• 2002.05a
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• pp.276-277
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• 2002

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.81-86
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• 2003

Electromigration of Sn-3.5Ag solder bump was investigated using flip chip specimens which consisted of upper Si chip and lower Si substrate. While the resistance of the flip chip sample did not almost change until the time right before the failure, the resistivity increased abruptly at the moment when complete failure of the solder joint occurred in the flip chip sample. At current densities of $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$, the activation energy for electromigration of the Sn-3.5Ag solder bump was characterized as ∼0.7 eV. Failure of the Sn-3.5Ag solder bump occurred at the solder/UBM interface due to the formation and propagation of voids at cathode side of the solder bump.