• Journal of information and communication convergence engineering
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• 제16권1호
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• pp.43-47
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• 2018

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.1-7
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• 2011

본 연구에서는 나노와이어 junctionless 트랜지스터의 문턱전압과 평탄전압을 위한 해석학적 모델링을 제시하였고 3차원 소자 시뮬레이션으로 검증하였다. 그리고 junctionless 트랜지스터의 소자설계 가이드라인을 설정하는 방법과 그 예를 제시하였다. 제시한 문턱전압과 평탄전압 모델은 3차원 시뮬레이션 결과와 잘 일치하였다. 나노와이어 반경과 게이트 산화층 두께가 클수록 또 채널 불순물 농도가 높을수록 문턱전압과 평탄전압은 감소하였다. 게이트 일함수와 원하는 구동전류/누설전류 비가 주어지면 나노와이어 반경, 게이트 산화층 두께, 채널 불순물 농도에 따른 junctionless 트랜지스터의 소자설계 가이드라인을 설정하였다. 나노와이어 반경이 작을수록 산화층의 두께가 얇을수록 채널 불순물 농도가 큰 소자를 설계할 수 있음을 알 수 있었다.

• 반도체디스플레이기술학회지
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• 제17권2호
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• pp.12-15
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• 2018

InSb (III-V compound semiconductor) is used for photodiode to detect the mid-wavelength infrared radiation. Generally the quantum efficiency of InSb IR FPAs(Focal Plane Arrays) is known to be determined by thickness of InSb and transmittance of anti-reflection coating layer. In this study, we confirmed that the C-V characteristics of detector array affects the quantum efficiency of the InSb IR FPAs. We fabricated the IR FPAs with various $V_{fb}$(flat band voltage) values and confirmed the tendency between the $V_{fb}$ value and quantum efficiency of the IR FPAs.

• 대한전기학회논문지
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• 제44권4호
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• pp.483-489
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• 1995

To investigate the mechanism generated by irradiation in the insulator layer irradiated MIS (Metal - Insulator - Semiconductor) device, the various types of MIS capacitors depending on insulator thickness, insulator types and implanted impurities are fabricated on the P-type wafer. MIS capacitors exposed by 1Mrad Co$^{60}$ .gamma.-ray are measured for flat band voltage and charge density shifts pre- and post-irradiation. The measuring results of post-irradiation show the flat band voltage shifting toward negative direction and charge density increasing regardless of parameters. This results have a good agreement with calculated data by computer simulation. Si$_{3}$N$_{4}$ layers have a good radiation-hardness than SiO$_{2}$ layers compared to the results of post-irradiation. Also, radiation-induced negative trap is discovered in the implanted insulator layer. Using numerical analysis, four continuty equations (conduction-band electrons continuity equation, valence-band holes continuity equation, trapped electrons continuity equation, trapped holes continuity equation) are solved and charge distributions according to the distance and Si-Insulator interface states are investigated.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.5-11
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• 2008

To study the effects of $H_2$ gas on AIN insulation thin film, we prepared AIN thin film on Si and GaAs substrate by means of reactive sputtering method using $H_2$ gas as an additives, With treatment conditions of $H_2$ gas AIN thin film shows variable electrical properties such as its crystallization and hysterisis affected to electrical property, As a results, AIN thin film fabricated on Si substrate post-treated with $H_2$ gas for 20 minutes shows much better an insulation property than that of pre-treated, And AIN film treated with $H_2$ gas comparing to non-treated AIN film shows a flat band voltage decreasment. But In GaAs substrate $H_2$ gas does not effect on the flat band voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1402-1404
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• 2009

The silicon nitride films for gate dielectric were deposited by catalytic chemical vapor deposition at low temperature (${\leq}200^{\circ}C$). The mixture of $SiH_4$, $NH_3$ and $H_2$ was used as source gases. The current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of the films were measured. The breakdown voltage and the flat band voltage shift of samples were improved by increase of the $NH_3$ contents and $H_2$ dilution ratio. The defect states were analyzed by photoluminescence (PL) spectra. As the defect states decreased, the breakdown voltage and the flat band voltage shift increased.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.333-335
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• 1997

This paper was performed to investigate the characteristic of the Pt-MIS(Metal Insulator Semiconductor) capacitor composed of the LPCVD nitride on the oxide for the hydrogen gas detection. Pt was used as catalytic metal for detecting the hydrogen gas and the flat band voltage shift was measured at various hydrogen concentration and catalytic metal thickness. We found the flat band voltage shift was proportional to the hydrogen concentration and catalytic metal thickness was little effect to the response time.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1264-1266
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• 1997

This paper reports the characteristic of tile MIS structure composed of the LPCVD nitride on the oxide for the hydrogen gas detection. Pt was used as catalytic metal for detecting the hydrogen gas and the flat band voltage shift was measured at various hydrogen concentration. We found the flat band voltage shift was proportional to the hydrogen concentration.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• 한국통신학회논문지
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• 제16권11호
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• pp.1179-1185
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• 1991

초박막 재산화 질화산화막을 $1050^{\circ}C-1100^{\circ}C$ 온도에서 20, 40초 동안 산소 분위기에서 램프 가열 방법의 급속 열처리 공정에 의해 형성 시켰다. 초박막의 전기적 특성은 누설전류, 항복전압, 시간종속 항복과 F-N 관통을 분석 하였다. 질화와 재산화 조건에 따른 전하포획의 의존성 즉 고전계 스트레스에 유기되는 항복전하량$(Q_{BD})$ 증가 여부와 평탄대역 전압이동$(\DeltaV_{FB})$을 연구하였다. 분석 결과에 의하면, 급속 열처리 재산화시 유전적 성질이 상당히 개선되었고, 항복전하량은 증가되었으며, 평탄대역전압은 감소 되었다.