• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Transactions of Materials Processing
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• v.32 no.6
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• pp.352-359
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• 2023

Recently, independent suspension systems have been applied not only to passenger cars but also to large commercial vehicles. Therefore, the need for research to domestically produce such independent suspensions for large commercial vehicles is gradually increasing. In this paper, we conducted research on the manufacturing technology of the relay lever, which are integral components of independent suspension systems for large commercial vehicles. Our goal was to reduce the flash volume generated during the forging process. The shape variables of the initial billet were adjusted to find proper forming conditions that could minimize flash volume while performing product forming smoothly. Shape variables were set as input variables and the flash volume was set as an output variable, and simulations were carried out to analytically predict the volume of the flash area for each variable condition. Based on the data obtained through numerical simulations, a regression model and an artificial neural network model were used to develop a prediction model that can easily predict the flash volume for variable conditions. For the corresponding prediction model, a goodness of-fit test was performed to confirm a high level of fit. By comparing and analyzing the two prediction models, the high level of fit of the ANN model was confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.546-553
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• 2015

Recently, flash cache is widely adopted as the performance accelerator of legacy storage systems. Unlike other cache media, flash cache should be carefully managed as it has peculiar characteristics such as long write latency and limited P/E cycles. In particular, we make two prominent observations that can be utilized in managing flash cache. First, a serious worn-out problem happens when the working-set of a system is beyond the capacity of flash cache due to excessively frequent cache replacement. Second, more than 50% of data has no hit in flash cache as it is a second level cache. Based on these observations, we propose a cache admission control policy that does not cache data when it is first accessed, and inserts it into the cache only after its second access occurs within a certain time window. This allows the filtering of data disruptive to flash cache in terms of endurance and performance. With this policy, we prolong the lifetime of flash cache 2.3 times without any performance degradations.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.6
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• pp.828-832
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• 2013

In this paper, numerical analysis was performed about whether the flash fire of loaded shells breaks out in the virtual combat vehicle according to sorts of the kinetic energy ammunition as the preceding research for vulnerability analysis inside the combat system by an external threaty ammunition. In this simulation, Autodyn program was used and the Lee-Tarver ignition and growth model was used to determine the flash fire outbreak. In this study, the kinetic energy ammunition was set of type A and type B in two kinds and the loaded shells was set of COMPB, TNT, PBX9404 and ANB. As a result, TNT and PBX9404 have much higher flash fire probability than COMPB in high explosive, ANB has very low flash fire probability.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• Proceedings of the Korea Water Resources Association Conference
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• 2022.05a
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• pp.146-146
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• 2022

A flash flood is one of the most hazardous natural events caused by heavy rainfall in a short period of time in mountainous areas with steep slopes. Early warning of flash flood is vital to minimize damage, but challenges remain in the enhancing accuracy and reliability of flash flood forecasts. The forecasters can easily determine whether flash flood is occurred using the flash flood guidance (FFG) comparing to rainfall volume of the same duration. In terms of this, the hydrological model that can consider the basin characteristics in real time can increase the accuracy of flash flood forecasting. Also, the predicted radar rainfall has a strength for short-lead time can be useful for flash flood forecasting. Therefore, using both hydrological models and radar rainfall forecasts can improve the accuracy of flash flood forecasts. In this study, FFG was applied to simulate some flash flood events in the Taehwa river basin by using of SURR model to consider soil moisture, and applied to the flash flood forecasting using predicted radar rainfall. The hydrometeorological data are gathered from 2011 to 2021. Furthermore, radar rainfall is forecasted up to 6-hours has been used to forecast flash flood during heavy rain in August 2021, Wulsan area. The accuracy of the predicted rainfall is evaluated and the correlation between observed and predicted rainfall is analyzed for quantitative evaluation. The results show that with a short lead time (1-3hr) the result of forecast flash flood events was very close to collected information, but with a larger lead time big difference was observed. The results obtained from this study are expected to use for set up the emergency planning to prevent the damage of flash flood.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.5
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.34-41
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• 2007

We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.710-716
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• 2008

This paper covers the performance evaluation of two flash memory-based file storages, NAND and NOR, which are the major flash types. To evaluate their performances, we set up separate file storages for the two types of flash memories on a PocketPC-based experimental platform. Using the platform, we measured and compared the I/O throughputs in terms of buffer size, amount of used space, and kernel-level write caching. According to the results from our experiments, the overall performance of the NAND-based storage is higher than that of NOR by up to 4.8 and 5.7 times in write and read throughputs, respectively. The experimental results show the relative strengths and weaknesses of the two schemes and provide insights which we believe assist in the design of flash memory-based file storages.