• The Journal of Korean Medicine
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• v.28 no.4
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• pp.74-85
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• 2007

Objective : In this study we wanted to confirm if proper stimulation and de-Qi of traditional Korean medical acupuncture could increase hot flash relief efficacy. Design : A randomized controlled, single blind study. We used two modalities of acupuncture, one with optimal stimulation [Study group; Korean medical acupuncture (TKMA)] and one with minimal stimulation [Control group; Minimal acupuncture (MA)]. Same acupoints [PC6(內關), HT8(少府), HT7(神門), LI4(合谷), ST36(足三里), SP6(三陰交), Ren4(關元)] were used in both groups. Fifty-two patients were treated twice a week for 8 weeks, and follow up was done after 4 weeks from the last treatment. Patients were checked hot flash VAS (visual analog scale), frequency and duration every time they visited. Results : Hot flash relief efficacy by 100mm hot flash VAS was obvious in both groups. Hot flash VAS scores of study group were smaller than the scores of control group at the early stage (3rd, $4^{th}$ and $8^{th}$ visit), but there wasn't a remarkable difference between study and control group at the end of the trial. Besides, diminution of hot flash VAS was faster and more even in the study group than control group by visualization using 'Box plot'. We compared frequency and duration of hot flash, 100mm sweating, palpitation, sleep disturbance VAS, and Kupperman Index, MENQOL, Patient's global assessment score. Both groups showed definite decrease from the baseline, but the difference was not statistically significant. There wasn't any adverse event. Hot flash relief efficacy was kept in most patients after 4 weeks' follow-up. Conclusion : Acupoint combination by Traditional Korean medical theory is effective on hot flashes and hot flash relief efficacy was faster and more even in optimal stimulation than minimal stimulation.

• Journal of Biomedical Engineering Research
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• v.19 no.3
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• pp.251-260
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• 1998

The Holter monitoring system is a widely used noninvasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we design a high performance intelligent holter monitoring system which is characterized by the small-sized and the low-power consumption. The system hardware consists of one-chip microcontroller(68HC11E9), ECG preprocessing circuit, and flash memory card. ECG preprocessing circuit is made of ECG preamplifier with gain of 250, 500 and 1000, the bandpass filter with bandwidth of 0.05-100Hz, the auto-balancing circuit and the saturation-calibrating circuit to eliminate baseline wandering, ECG signal sampled at 240 samples/sec is converted to the digital signal. We use a linear recursive filter and preprocessing algorithm to detect the ECG parameters which are QRS complex, and Q-R-T points, ST-level, HR, QT interval. The long-term acquired ECG signals and diagnostic parameters are compressed by the MFan(Modified Fan) and the delta modulation method. To easily interface with the PC based analyzer program which is operated in DOS and Windows, the compressed data, that are compatible to FFS(flash file system) format, are stored at the flash memory card with SBF(symmetric block format).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.168-174
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• 2012

Flash is the most popular 2D animation and game development software, supporting vector and media technology at the core, which enables the development of small and pithy games. It is widely used in Web animation, courseware, TV commercials, game development, and other works of design. In this paper, we propose a control movement function and auxiliary functions for an alpine skiing game based on ActionScript 3.0. The control movement function is designed with moving phases (i.e., free fall, sliding, projectile, and landing). The auxiliary functions include drawing path, start/restart movement, and saving the highest score. In addition, for the visual design of our game, we designed animations in connection with a character and background. In order to facilitate testing the friction, users can input a chosen friction value. Without user input, the friction default is set at 0.97.

• Journal of Power Electronics
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• v.10 no.6
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• pp.643-646
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• 2010

An interactive web-based teaching tool for a power semiconductor course at the University of Central Florida is presented in this paper. A novel approach is introduced using Technology Aided Design Tools (TCAD) to generate time-lapsed 2D semiconductor device cross-section embedded in a webpage using $Adobe^{(R)}$ Flash (web design tool) platform to create interactive movies that demonstrate complex device physical phenomenon. Students can step through the interactive movies forward, backward, pausing, or looping. Each step represents a giving bias condition. Current-voltage plots are represented along with the semiconductor device and a visual point is placed on the IV curve to indicate the current bias conditions. The changes are then reflected in the 2D cross-section movie area and the IV plot. This tool was implemented in a classroom setting to augment the lectures or for discovery learning.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.7
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• pp.515-519
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• 2009

As the application fields of sensor nodes are getting diverse these days, it is required to have a way of collecting various data that is suitable for these application fields. In the case that the real-time surveillance over the data is unnecessary, present data collecting methods, which collect and transfer the data directly, can cause a waste of energy and data loss, A new method that store the collected data in a local storage and acquire them by query later on is required for nonreal-time applications. NAND flash has energy efficiency and large capacity so it is suitable for sensor nodes, Sensor nodes support 4-10 KBytes small sized memory and it is hard to build an effective file system since NAND Flash doesn't support overwriting NAND flash. This paper discusses an implementation of NAND Flash file system in sensor node environments. The file system makes long-term data collecting possible by reducing transmission cost. It is expected that this file system will play a central role in sensor network environments as it can be applied to various fields which call for long term data collecting.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.1-8
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• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.885-891
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• 2012

The synchronous flash of a marine lantern, differentiated from the flash pattern of other risk indicators, supports the safe sailing of vessels. General marine lanterns flash according to the flash protocol through sensing the day and the night. Thus, there can be time error over time and the marine lantern does not synchronously flash as a whole. To resolve this problem, this study designed LED marine lantern based on constant-current system using synchronous flash technique enabling all marine lanterns to keep its time based on GPS satellite time. Also we suggested a radiation method with an effective heat emission performance in the restricted and closed space of a marine lantern.