A Design of Constructing Diagram Repository for UML Diagram Tools (UML 다이어그램 도구를 위한 다이어그램 정보의 구축과 설계)
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- Journal of the Korea Institute of Information and Communication Engineering
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- v.24 no.2
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- pp.244-251
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- 2020
This paper presents a design of the Meta-Class Repository (MCR) which maintain syntactically analyzed and structured meta-class information from UML diagrams, and then proposes 'meta-class,' also known as super-class, to construct structured information analyzed syntactically. The MCR is a collection of these meta-classes which contains the information extracted from diagrams. This paper also presents a design of the Code Generation Engine (CGE) which roles generating codes corresponding classes from UML diagrams based on the MCR maintaining a collection of meta-classes which is syntactically-analyzed and constructed in previous process. The logics of CGE are designed to generate codes collaborated with MCR and CGE with integration. The logics of CGE mechanism is presented with the form of finite state machine to present the algorithms of code generation formally and have the advantages of simplicity and easiness in development.
Piecewise Integrated Composite (PIC) is a new concept to design composite structures of multiple stacking angles both for in-plane direction and through the thickness direction in order to improve stiffness and strength. In the present study, PIC beam was suggested based on 3D training data instead of 2D data, which did offer a limited behavior of beam characteristics, with enhancing the stiffness accompanied by reduced tip deformation. Generally training data were observed from the designated reference finite elements, and preliminary FE analysis was conducted with respect to regularly distributed reference elements. Also triaxiality values for each element were obtained in order to categorize the loading state, i.e. tensile, compressive or shear. The main FE analysis was conducted to predict the mechanical characteristics of the PIC beam.
This is the third part of the four-part paper describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the X.25 protocol connecting packet mode data terminal equipments(PDTE's) with data circuit terminating equipments(DCE's). In the KORNET, the X.25 protocol has been implemented on the line processing module-A(LPMA) of the network node processor(NNP). In the implementation of X.25, we have divided the software module according to the service function, and have determined the the rules that interact between the modules. Each layer protocol has been developed using the technique of the finite state machine. Before the actual coding of softwares, we hafve used formal software development tools based on the specification and description language (SDL) and program design languate (PDL) recommended by the CCITT. In addition, for the efficient operation of the X.25 protocol system we have analyzed the system performance and the service scheduling method of each module. The results will also be given.
The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.
Natural language processing (NLP) is an emerging research area in which we study how machines can be used to perceive and alter the text written in natural languages. We can perform different tasks on natural languages by analyzing them through various annotational tasks like parsing, chunking, part-of-speech tagging and lexical analysis etc. These annotational tasks depend on morphological structure of a particular natural language. The focus of this work is part-of-speech tagging (POS tagging) on Hindi language. Part-of-speech tagging also known as grammatical tagging is a process of assigning different grammatical categories to each word of a given text. These grammatical categories can be noun, verb, time, date, number etc. Hindi is the most widely used and official language of India. It is also among the top five most spoken languages of the world. For English and other languages, a diverse range of POS taggers are available, but these POS taggers can not be applied on the Hindi language as Hindi is one of the most morphologically rich language. Furthermore there is a significant difference between the morphological structures of these languages. Thus in this work, a POS tagger system is presented for the Hindi language. For Hindi POS tagging a hybrid approach is presented in this paper which combines "Probability-based and Rule-based" approaches. For known word tagging a Unigram model of probability class is used, whereas for tagging unknown words various lexical and contextual features are used. Various finite state machine automata are constructed for demonstrating different rules and then regular expressions are used to implement these rules. A tagset is also prepared for this task, which contains 29 standard part-of-speech tags. The tagset also includes two unique tags, i.e., date tag and time tag. These date and time tags support all possible formats. Regular expressions are used to implement all pattern based tags like time, date, number and special symbols. The aim of the presented approach is to increase the correctness of an automatic Hindi POS tagging while bounding the requirement of a large human-made corpus. This hybrid approach uses a probability-based model to increase automatic tagging and a rule-based model to bound the requirement of an already trained corpus. This approach is based on very small labeled training set (around 9,000 words) and yields 96.54% of best precision and 95.08% of average precision. The approach also yields best accuracy of 91.39% and an average accuracy of 88.15%.
IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.
A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.
Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.
The wall shear stress in the vicinity of end-to end anastomoses under steady flow conditions was measured using a flush-mounted hot-film anemometer(FMHFA) probe. The experimental measurements were in good agreement with numerical results except in flow with low Reynolds numbers. The wall shear stress increased proximal to the anastomosis in flow from the Penrose tubing (simulating an artery) to the PTFE: graft. In flow from the PTFE graft to the Penrose tubing, low wall shear stress was observed distal to the anastomosis. Abnormal distributions of wall shear stress in the vicinity of the anastomosis, resulting from the compliance mismatch between the graft and the host artery, might be an important factor of ANFH formation and the graft failure. The present study suggests a correlation between regions of the low wall shear stress and the development of anastomotic neointimal fibrous hyperplasia(ANPH) in end-to-end anastomoses. 30523 T00401030523 ^x Air pressure decay(APD) rate and ultrafiltration rate(UFR) tests were performed on new and saline rinsed dialyzers as well as those roused in patients several times. C-DAK 4000 (Cordis Dow) and CF IS-11 (Baxter Travenol) reused dialyzers obtained from the dialysis clinic were used in the present study. The new dialyzers exhibited a relatively flat APD, whereas saline rinsed and reused dialyzers showed considerable amount of decay. C-DAH dialyzers had a larger APD(11.70
The wall shear stress in the vicinity of end-to end anastomoses under steady flow conditions was measured using a flush-mounted hot-film anemometer(FMHFA) probe. The experimental measurements were in good agreement with numerical results except in flow with low Reynolds numbers. The wall shear stress increased proximal to the anastomosis in flow from the Penrose tubing (simulating an artery) to the PTFE: graft. In flow from the PTFE graft to the Penrose tubing, low wall shear stress was observed distal to the anastomosis. Abnormal distributions of wall shear stress in the vicinity of the anastomosis, resulting from the compliance mismatch between the graft and the host artery, might be an important factor of ANFH formation and the graft failure. The present study suggests a correlation between regions of the low wall shear stress and the development of anastomotic neointimal fibrous hyperplasia(ANPH) in end-to-end anastomoses. 30523 T00401030523 ^x Air pressure decay(APD) rate and ultrafiltration rate(UFR) tests were performed on new and saline rinsed dialyzers as well as those roused in patients several times. C-DAK 4000 (Cordis Dow) and CF IS-11 (Baxter Travenol) reused dialyzers obtained from the dialysis clinic were used in the present study. The new dialyzers exhibited a relatively flat APD, whereas saline rinsed and reused dialyzers showed considerable amount of decay. C-DAH dialyzers had a larger APD(11.70