• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of information and communication convergence engineering
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• v.15 no.3
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• pp.160-164
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• 2017

Public key cryptography (PKC) is the basic building block for the cryptography applications such as encryption, key distribution, and digital signature scheme. Among many PKC, elliptic curve cryptography (ECC) is the most widely used in IT systems. Recently, very efficient Montgomery-Twisted-Edward (MoTE)-ECC was suggested, which supports low complexity for the finite field arithmetic, group operation, and scalar multiplication. However, we cannot directly adopt the MoTE-ECC to new PKC systems since the cryptography is not fully evaluated in terms of performance on the Internet of Things (IoT) platforms, which only supports very limited computation power, energy, and storage. In this paper, we fully evaluate the MoTE-ECC implementations on the representative IoT devices (16-bit MSP processors). The implementation is highly optimized for the target platform and compared in three different factors (ROM, RAM, and execution time). The work provides good reference results for a gradual transition from legacy ECC to MoTE-ECC on emerging IoT platforms.

• Bulletin of the Korean Mathematical Society
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• v.32 no.2
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• pp.337-342
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• 1995

A semiring is a binary system $(S, +, \times)$ such that (S, +) is an Abelian monoid (identity 0), (S,x) is a monoid (identity 1), $\times$ distributes over +, 0 $\times s s \times 0 = 0$ for all s in S, and $1 \neq 0$. Usually S denotes the system and $\times$ is denoted by juxtaposition. If $(S,\times)$ is Abelian, then S is commutative. Thus all rings are semirings. Some examples of semirings which occur in combinatorics are Boolean algebra of subsets of a finite set (with addition being union and multiplication being intersection) and the nonnegative integers (with usual arithmetic). The concepts of matrix theory are defined over a semiring as over a field. Recently a number of authors have studied various problems of semiring matrix theory. In particular, Minc [4] has written an encyclopedic work on nonnegative matrices.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.561-566
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• 2013

We propose an efficient exponentiation method which is resistant against some side channel attacks in $T_2(p)$, Torus-Based-Cryptosystem. It is more efficient than the general exponentiation method in $T_2(p)$ and is resistant against SPA by using that the difference of squaring and multiplication costs is negligible. Moreover, we can randomize a message in exponentiation step using the characteristic of quotient group which naturally protects against the first DPA.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.741-744
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• 1999

In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q＞ 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• Journal of Communications and Networks
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• v.12 no.1
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• pp.1-4
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• 2010

As a countermeasure to simple power attack, the unified point addition codes for the elliptic curve cryptosystem were introduced. However, some authors proposed a different kind of power attacks to the codes. This power attack uses the observation that some internal operations in the codes behave differently for addition and doubling. In this paper, we propose a new countermeasure against such an attack. The basic idea of the new countermeasure is that, if one of the input points of the codes is transformed to an equivalent point over the underlying finite field, then the code will behave in the same manner for addition and doubling. The new countermeasure is highly efficient in that it only requires 27(n-1)/3 extra ordinary integer subtractions (in average) for the whole n-bit scalar multiplication. The timing analysis of the proposed countermeasure is also presented to confirm its SPA resistance.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.23 no.6 s.165
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• pp.988-1000
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• 1999

An experimental study is presented for the effect of number of terms of a pewee series type stress function on stress analysis around a hole in tensile loaded plate. The hybrid method coupling photoelastsic data inputs and complex variable formulations involving conformal mappings and analytical continuity is used to calculate tangential stress on the boundary of the hole in uniaxially loaded, finite width tensile plate. In order to measure isochromatic data accurately, actual photoelastic fringe patterns are two times multiplied and sharpened by digital image processing. For qualitative comparison, actual fringes are compared with calculated ones. For quantitative comparison, percentage errors and standard deviations with respect to percentage errors are caculated for all measured points by changing the number of terms of stress function. The experimental results indicate that stress concentration factors analyzed by the hybrid method are accurate within three percent compared with ones obtained by theoretical and finite element analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.469-472
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• 2003

The computational cost of encryption is a barrier to wider application of a variety of data security protocols. Virtually all research on Elliptic Curve Cryptography(ECC) provides evidence to suggest that ECC can provide a family of encryption algorithms that implementation than do current widely used methods. This efficiency is obtained since ECC allows much shorter key lengths for equivalent levels of security. This paper suggests how improvements in execution of ECC algorithms can be obtained by changing the representation of the elements of the finite field of the ECC algorithm. Specifically, this research compares the time complexity of ECC computation eve. a variety of finite fields with elements expressed in the polynomial basis(PB) and normal basis(NB).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.