• 정보보호학회논문지
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• 제9권4호
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• pp.3-10
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• 1999

유한체(Galois fields)가 타원곡선 암호법 coding 이론 등에 응용되면서 유한체의 연 산은 더많은 관심의 대상이 되고 있다. 유한체의 연산은 표현방법에 많은 영향을 받는다. 즉 최적 정규기 저는 하드웨 어 구현에 용이하고 Trinomial을 이용한 다항식 기저는 소프트웨어 구현에 효과적이다. 이논문에서는 새로운 변형된 다항식 기저를 소개하고 AOP를 이용한 경우 하드웨어 구현에 효과적인 최 적 정규기저와 의 변환이 위치 변화로 이루어지고 또한 이것을 바탕으로 한 유한체의 연산이 소프트웨어적 으로 효율적 임을 보인다. More concerns are concentrated in finite fields arithmetic as finite fields being applied for Elliptic curve cryptosystem coding theory and etc. Finite fields arithmetic is affected in represen -tation of those. Optimal normal basis is effective in hardware implementation and polynomial field which is effective in the basis conversion with optimal normal basis and show that the arithmetic of finite field with the basis is effective in software implementation.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• 대한임베디드공학회논문지
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• 제11권4호
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 한국전자통신학회논문지
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• 제8권8호
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• pp.1207-1212
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• 2013

유한체 연산은 부호이론과 암호학에 널리 쓰이고 있으므로, 유한체 연산의 복잡도를 낮출 수 있는 연산기가 절실하게 필요하다. 그런데 연산기의 복잡도는 유한체의 원소를 표현하는 방법에 달려있다. 복잡도를 줄이기 위해서, 지금까지 알려진 원소를 표현하는 가장 좋은 방법이 최적정규기저를 사용하는 것이다. 본 논문에서는 최적정규기저로 표현된 원소의 곱셈시에 구축되는 곱셈행렬의 1의 개수를 최소화하는 알고리즘을 개발하여 시간과 공간을 최소화하는 곱셈기를 제안하고자 한다.

• 전자공학회논문지
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• 제53권2호
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• pp.70-75
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• 2016

본 논문에서는 다항식에 기초하여 유한체상의 P=2인 경우의 효율적인 곱셈기를 구성하는 방법을 제안하였다. 제안한 곱셈기 회로는 다항식의 연산부와 mod F(${\alpha}$) 연산부, 모듈러 연산부로 구성된다. 또한, 이들 각 연산부는 모듈 구조를 가지므로 m의 확장에 따른 회로 구성이 용이하며 회로 구성에 사용한 소자는 AND 게이트와 XOR 게이트만으로 구성하여 정규성, 확장성이 용이하며 이를 기반으로 VLSI화에 적합하다. 제안한 곱셈기는 기존의 곱셈기에 비해 좀 더 콤펙트, 규칙적, 정규성과 확장성이 용이하며 최근의 IoT 환경에서의 여러 분야에 적용 및 응용이 가능할 것이다.

• Journal of information and communication convergence engineering
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• 제8권3호
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• pp.317-322
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• 2010

This paper presents an algorithm generating inverse element over finite fields GF($3^m$), and constructing method of inverse element generator based on inverse element generating algorithm. An inverse computing method of an element over GF($3^m$) which corresponds to a polynomial over GF($3^m$) with order less than equal to m-1. Here, the computation is based on multiplication, square and cube method derived from the mathematics properties over finite fields.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 대한전자공학회논문지
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• 제15권5호
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• pp.29-33
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• 1978

본 논문에서는 Galois 스윗칭함수를 구하기 위해서 임의의 유한체상에서 정의되는 Galois 체의 성질을 설명하였고, 임의의 유한체상에서의 연산방법을 밝혔다. 고리고 Lagrange 보간법에 의한 다항식이 유한체상에서 전개될 수 있음을 증명하였다 이 결과를 적용하여 단일변수를 갖는 Galois스윗칭 함수를 유도하고 다치논리회로를 실현하였다.

• 대한전자공학회논문지
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• 제25권5호
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.