• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.157-172
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• 2005

기존 단말기에 Fine Pitch (0.3mm) WLCSP를 개발/적용해 봄으로써 SMT 조립 한계로 인식되고 있는 Pitch인 0.4mm이하의 접속 기술을 검증함. Set Maker 입장에서 Fine Pitch를 가진 Customized Package를 적용할 경우, Design 단계에서부터 부품, 기판, 조립공법, Infrastructure등을 동시에 검토해야 함. 이동단말의 소형화/박형화 경쟁이 가속화 되는 가운데 Package Pitch만을 고려해 볼 때, 2006년에는 0.4mm Pitch를 가진 BGA의 적용이 확대 될 것으로 예상되며 일부 제품에서 0.3mm Pitch Package의 적용도 예상됨.

• 마이크로전자및패키징학회지
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• 제21권3호
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• pp.1-6
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• 2014

차세대 전자소자는 입출력(I/O) 핀 수의 증가, 전력소모의 감소, 소형화 등으로 인해 fine-pitch 배선 시스템이 요구되고 있다. Fine-pitch 특히 10 um 이하의 fine-pitch에서는 기존의 무연솔더나 Cu pillar/solder cap 구조를 사용할 수 없기 때문에 Cu-to-Cu bumpless 배선 시스템은 2D/3D 소자 구조에서 매우 필요한 기술이라 하겠다. Bumpless 배선 기술로는 BBUL 기술, 접착제를 이용한 WOW의 본딩 기술, SAB 기술, SAM 기술, 그리고 Cu-to-Cu 열압착 본딩 기술 등이 연구되고 있다. Fine-pitch Cu-to-Cu interconnect 기술은 연결 방법에 상관없이 Cu 층의 불순물을 제거하는 표면 처리 공정, 표면 활성화, 표면 평탄도 및 거칠기가 매우 중요한 요소라 하겠다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• 소성∙가공
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• 제19권8호
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• pp.474-479
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• 2010

Newly suggested hybrid LED package can reduce the number of LED processes and enhance light efficacy in virtue of its integrated optical patterns. Square-type pyramid pattern was chosen for the integrated optical pattern in this study, and it was proved that the pattern enhances illuminance about three times and luminance about two and half times by optical simulation. Square-type pyramid patterns of 0.02mm height and 0.04mm pitch were successively machined on a copper mold which is necessary for imprinting the integrated pattern. Hybrid LED package with integrated optical pattern will be manufactured with ultra-fine machined mold in future study.

• Journal of Welding and Joining
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• 제27권3호
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• pp.17-22
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• 2009

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• Journal of electromagnetic engineering and science
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• 제11권1호
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• 한국정밀공학회지
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• 제16권3호통권96호
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.83-90
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• 2017

본 연구에서는 미세피치 패키지 적용을 위한 기초 실험으로 thin ENEPIG(Electroless Nickel Electroless Palladium Immersion Gold) 도금층을 형성하여 솔더링 특성을 평가하였다. 먼저, Sn-3.0Ag-0.5Cu (SAC305) 솔더합금에 대한 thin ENEPIG 도금층의 젖음 특성이 평가되었으며, 순차적인 솔더와의 반응에 대한 계면반응 및 솔더볼 접합 후 고속 전단 시험을 통한 접합부 기계적 신뢰성이 평가되었다. 젖음성 시험에서 침지 시간이 증가함에 따라 최대 젖음력은 증가하였으며, 5초의 침지 시간 이후에는 최대 젖음력이 일정하게 유지되었다. 초기 계면 반응 동안에는 $(Cu,Ni)_6Sn_5$ 금속간화합물과 P-rich Ni 층이 SAC305/ENEPIG 계면에서 관찰되었다. 연장된 계면반응 후에는 P-rich Ni 층이 파괴 되었으며, 파괴된 P-rich Ni 층 아래에는 $(Cu,Ni)_3Sn$ 금속간화합물이 생성되었다. 고속 전단 시험의 경우, 전단속도가 증가함에 따라 취성 파괴율이 증가하였다.