• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Smart Structures and Systems
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• v.3 no.1
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• pp.69-88
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• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.9
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• pp.43-51
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• 2010

Speed, accuracy and smoothness are the important properties of pan-tilt camera. In the case of a high ratio zoom lens system, low vibration characteristic is a crucial point in driving pan-tilt mechanism. In this paper, a novel micro-stepping controller with a function of reducing vibration was designed using field programmable gate arrays (FPGA) technology for high zoom ratio pan-tilt camera. The proposed variable reference current (VRC) control scheme reduces vibration decently and optimizing coil current in order to prevent the step motor from occurring missing steps. By employing VRC control scheme, the vibration in low speed could be significantly minimized. The proposed controller can also make very high speed of 378kpps micro-step driving, and increase maximum acceleration in motion profiles.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Journal of applied mathematics & informatics
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• v.39 no.5_6
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Journal of Advanced Navigation Technology
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• v.10 no.1
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• pp.70-78
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• 2006

This paper has addressed the scheme to design single rate Rate Adaptive Shaper (srRAS) proposed in RFC2963. srRAS is the shaper used in conjugation with downstream single rate Three Color Marker (srTCM) described in RFC269. it is tail-drop First Input First Out (FIFO) queue that is drained at a variable rate. srTCM meters IP packet streams from srRAS and marks its packets to be either green, yellow, or red. This shaper has been proposed to use at the ingress of differentiated services networks providing AF PHB. And then srRAS can reduce the burstiness of the upstream traffic of srTCM. This paper addresses algorithm, architecture of srRAS, and the scheme to implement srRAS using Field-Programmable Gate Arrays (FPGA) and the related technology.