• 한국정보과학회논문지:시스템및이론
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• 제34권12호
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays는 사용자가 프로그램이 가능한 혁신적인 대규모 집적 회로이며 값싸고 빠르게 주문자가 원하는 VLSI 구현할 수 있는 장점을 가지고 있다. 그러나 특정 목적의 프로그램의 속도가 증가했을 때 FPGA가 연산하는 동안의 전력 소모와 연결선의 지연이 FPGA를 프로그램 하는데 중요한 문제점이 된다. 특히 기존 구조에서 사용되는 내부연결선이 전체 FPGA의 전력 중 65%를 소모한다. 이로 인하여 내부연결선이 전력 소모에 큰 영향을 주기 때문에 배선 시 연결선의 길이와 블록 간의 연결선을 줄임으로써 전력 소모를 줄일 수 있다. 배선 시 내부연결선을 줄이기 위한 방안으로 3차원 FPGA가 제안되었다. 하지만 구조의 복잡해짐으로써 오히려 스위치에서 물리적인 연결선들은 더욱 증가하고 스위치의 면적이 증가하는 문제점을 가지게 되었다. 본 논문에서는 복잡성을 낮추어서 물리적인 내부 연결선의 길이를 줄이고, 배선시의 연결선의 길이를 3차원 FPGA만큼 줄일 수 있는 FPGA구조를 제안한다. 그리고 ISE 의 FPGA Editor와 배선 시 길이를 예측하는 프로그램을 사용하여 Xilinx사의 Virtex II FPGA와 3D FPGA의 연결선 구성을 비교한다.

• Smart Structures and Systems
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• 제3권1호
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• pp.69-88
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• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

• 한국정밀공학회지
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• 제27권9호
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• pp.43-51
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• 2010

Speed, accuracy and smoothness are the important properties of pan-tilt camera. In the case of a high ratio zoom lens system, low vibration characteristic is a crucial point in driving pan-tilt mechanism. In this paper, a novel micro-stepping controller with a function of reducing vibration was designed using field programmable gate arrays (FPGA) technology for high zoom ratio pan-tilt camera. The proposed variable reference current (VRC) control scheme reduces vibration decently and optimizing coil current in order to prevent the step motor from occurring missing steps. By employing VRC control scheme, the vibration in low speed could be significantly minimized. The proposed controller can also make very high speed of 378kpps micro-step driving, and increase maximum acceleration in motion profiles.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Journal of applied mathematics & informatics
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• 제39권5_6호
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• Nuclear Engineering and Technology
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• 제55권8호
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제5권3호
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• International Journal of Aeronautical and Space Sciences
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• 제18권4호
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• 한국항행학회논문지
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• 제10권1호
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• pp.70-78
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• 2006

본 논문은 RFC2963에서 제안된 single rate Rate adaptive Shaper (srRAS)를 설계한 것이다. srRAS는 RFC2693에서 제안된 하향의 single rate Three Color Marker (srTCM)과 함께 사용된 쉐이퍼이다. 그것은 가변 속도로 출력되는 tail-drop FIFO (First Input First Out) 큐이다. srTCM은 srRAS로부터의 IP 패킷 스트림을 측정한 후 그 패킷을 green, yellow, 또는 red로 마킹해 준다. 이 쉐이퍼는 AF PHB (Per Hop Behavior)를 제공하는 DS (Differentiated Service) 네트워크의 입력에서 사용되도록 제안되었다. 그리고 srRAS는 srTCM의 상향 트래픽의 버스트성을 줄여줄 수 있다. 본 논문은 srRAS의 알고리즘, 구조, 그리고 FPGA 및 관련 기술을 통하여 구현할 수 있는 방안을 언급하였다.