• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.813-819
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• 2008

In this paper, we implemented a real-time system which displays 3-dimensional (3D) stereoscopic image with stereo camera. The system consists of a set of stereo camera, FPGA board, and 3D stereoscopic LCD. Two CMOS image sensor were used for the stereo camera. FPGA which processes video data was designed with Verilog-HDL, and it can accommodate various resolutional videos. The stereoscopic image is configured by two methods which are side-by-side and up-down image configuration. After the left and right images are converted to the type for the stereoscopic display, they are stored into SDRAM. When the next frame is inputted into FPGA from two CMOS image sensors, the previous video data is output to the DA converter for displaying it. From this pipeline operation, the real-time operation is possible. After the proposed system was implemented into hardware, we verified that it operated exactly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2285-2291
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• 2011

In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

• ETRI Journal
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• v.29 no.3
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• pp.363-370
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• 2007

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2016.06a
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• pp.258-259
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• 2016

일반적으로 UHD 방송 편집 시스템에서 UHD 영상의 데이터양이 막대하기 때문에 실시간 전송을 위해 코덱과 함께 압축하여 편집 서버로 혹은 편집 서버로부터 스트림 형태로 전송한다. BT.1120 형태로 전송 송출된 SDI (Serial Digital Interface) 내장 음향 데이터는 영상과 달리 보조 데이터 영역에 다른 메타 데이터들과 함께 합성되어 전송 송출되기 때문에 추출 및 합성이 상대적으로 어렵다. 특히 재생을 위해서는 영상 코덱으로부터의 출력 영상과의 동기를 고려해야 하고 음향 데이터를 BT.1120 표준에 맞춰 보조 데이터 영역에 합성해야하기 때문에 개발에 어려움이 있다. 이에 본 논문은 UHD 영상/음향 데이터의 실시간 획득/재생 시스템에서의 SDI 내장 음향 데이터의 추출 및 합성을 위한 FPGA (Field Programmable Gate Array) 기반 하드웨어 플랫폼을 제안하였다. 또한, 이를 위한 음향 데이터 추출 로직과 합성 로직을 HDL(Hardware Design Language) 설계하여 FPGA 내에 탑재하고 카메라/디스플레이/편집 서버와 통합하였다. 시험 결과 4K 60fps 데이터에서 정상적으로 영상과 음향을 분리/획득 및 합성/재생하였다.

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.199-205
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• 2016

We present a novel schematic using a 3-dB coupler to transmit radiofrequency (RF) power to two receivers selectively. Whereas previous multiple receiver supporting schemes used hardware-switched methods, our scheme uses a soft power-allocating method, which has the advantage of variable power allocation in real time to each receiver. Using our scheme, we can split the charging area and focus the RF power on the targeted areas. We present our soft power-allocating method in three main points. First, we propose a new power distribution hardware structure using a FPGA (field-programmable gate array) and a 3-dB coupler. It can reconfigure the transmitting power to two receivers selectively using accurate FPGA-controlled signals with the aid of software. Second, we propose a power control method in our platform. We can variably control the total power of transmitter using the DC bias of the drain input of the amplifier. Third, we provide the possibility of expansion in multiple systems by extending these two wireless power transfer systems. We believe that this method is a new approach to controlling power amplifier output softly to support multiple receivers.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.